SERIES PMC408 PCI MEZZANINE CARD 32-CHANNEL DIGITAL I/O MODULE
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2.
Determine the IRQ line assigned to the PMC408 during system
configuration (read configuration register number 15).
3.
Set up the system interrupt vector for the appropriate interrupt.
4.
Unmask the IRQ in the system interrupt controller.
5.
The interrupt service routine pointed to by the vector set up in
step 3 starts.
6.
Interrupt service routine determines if the PMC408 has a
pending interrupt request by reading the Interrupt pending bit-1
of the Interrupt Register.
7. Example of Generic Interrupt Handler Actions:
A. Disable the interrupting channel(s) by writing a “0” to the
appropriate bits in the PMC408 Interrupt Enable Register.
B. Clear the interrupting channel(s) by writing a “1” to the
appropriate bits in the PMC408 Interrupt Status Register.
C. Enable the interrupting channel(s) by writing a “1” to the
appropriate bits in the PMC408 Interrupt Enable Registers
at Base A 210H. Also, write a “1” to bit-0 of the
Interrupt Register at Base A 000H.
8. Write
“End-Of-Interrupt”
command to systems interrupt
controller.
9.
If the PMC408’s interrupt stimulus has been removed, the
interrupt cycle is completed and the board holds the INTA#
inactive.
4.0 THEORY OF OPERATION
This section describes the basic functionality of the circuitry
used on the board. Refer to the Block Diagram shown in Drawing
4501-866 as you review this material.
INPUT/OUTPUT
The field I/O interface to the carrier board is provided through
connector P1 (refer to Table 2.1). Field I/O points are NON-
ISOLATED. This means that the field return and logic common
have a direct electrical connection to each other. As such, care
must be taken to avoid ground loops (see Section 2 for connection
recommendations). Ignoring this effect may cause operation errors,
and with extreme abuse, possible circuit damage. Refer to
Drawings 4501-867 & 4501-868 for example I/O and grounding
connections.
A Field Programmable Gate Array (FPGA) is used to generate
all the logic necessary to operate the board. With respect to input
acquisition, the interrupt channels drive the FPGA through 8
individual buffers (channels 0-7 only). The input buffers of the other
24 channels are selectively enabled and drive the data bus directly.
The field input signals are tied to the inputs of these buffers via a
100K
Ω
series connected resistor which limits the input current (but
raises the tandem output’s off-state drain current). Additionally, the
buffer inputs are clamped to +4.7V (generated from the +12V supply
to mi5V loading). The input signal threshold is TTL
compatible. The typical threshold is 1.5V DC with 200mV of
hysteresis.
For output control, 32 open-drain outputs are connected in
tandem with 32 input buffers to each I/O channel. The outputs are
the open drains of individual mosfets. The gates of the mosfets are
driven by the FPGA. The sources of these mosfets are connected
in common. This configuration provides up to 32 low-side switches
for digital control. Writing a ‘1’ to the output will turn the switch ON
(closed-circuit), a ‘0’ will turn it OFF (open-circuit). Since the input
buffers are connected in tandem with the output mosfets, efficient
loopback monitoring of the output state can be accomplished by
reading the input channel registers.
With respect to output control, the 100K
Ω
input buffer resistors
in combination with +4.7V voltage clamps will tend to increase the
off-state drain current with increased drain voltage (up to 0.5mA at
60V). This is due to the fact that the input buffer circuitry and output
mosfet drain circuitry are connected in tandem to the same I/O pin.
If this presents a problem for your application, then you should
consider separating the inputs and outputs by using multiple boards.
Output operation is considered ‘Fail-safe’. That is, the outputs
are always OFF upon power-up reset, and are automatically cleared
following a system software reset. This is done for safety reasons to
ensure reliable control of the output state under all conditions.
Further, unlike some competitive units, output gate pulldowns are
included to ensure that the outputs do not turn on momentarily when
output load power is applied with no power to the PMC module.
The output mosfets employed are rated for a much higher
current than specified. However, the field connector and cabling
used are only rated to 1A per pin (limiting a single channel to 1A).
For compatibility with other PMC models, 10 pins have been
reserved for ground return (hence; the 10A total current limitation
placed on this module). The low R
dsON
of the output mosfets will
ensure TTL-level compatible logic-low output signals even at high
(1A) output currents.
The output mosfets include an integrated zener diode between
the drain and the source. This provides output voltage clamp
protection to 60V. The tandem input channel is also rated to 60V.
However, when driving inductive loads such as relay coils, you
should always place a shunt diode across the load to shunt the
reverse EMF that develops across the coil when the current through
it is turned off (refer to Section 2 and see Drawing 4501-867 for an
example of this type of protection).
Since the input buffer and output mosfet circuitry share an I/O
pin, inputs and outputs may be intermixed in any combination.
Further, by providing an input channel for each output, efficient
loopback monitoring of the output state can be easily accomplished
(see Drawing 4501-868).
Digital input channels of this model can be configured to
generate interrupts for Change-Of-State (COS) and input level
(polarity) match conditions at selected input channels (channels 0-7
only). The interrupt release mechanism employed is RORA
(Release On Register Access).
PCI INTERFACE LOGIC
The PCI bus interface logic is imbedded within the FPGA. This
logic includes support for PCI commands, including: configuration
read/write, and memory read/write. In addition, the PCI target
interface performs parity error detection, uses a single 4K base
address register, and implements target abort, retry, and disconnect.
The PMC408 logic also implements interrupt requests via interrupt
line INTA#. J1 and J2 connectors also provide
±
12V and +5V to
power the module (-12V is not used).
A PCI bus read of the PMC module will initially terminate with a
retry. While the read data is moved to the read register (typically
1000ns), continued retries will result in retry terminations. The retry
