Acromag AMVE9675-4E, Руководство пользователя

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INDUSTRIAL I/O PACK SERIES AVME9675 VME64x 6U CARRIER BOARD
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Pin assignments for these connectors are defined by the IP
module specification and are shown in Table 2.2:
Table 2.2: Standard IP Logic Interface Connections (P4,6,8,10)
Pin Description Number Pin Description Number
GND 1 GND 26
CLK 2 +5V 27
Reset* 3 R/W* 28
D00 4 IDSEL* 29
D01 5 DMAReq0* 30
D02 6 MEMSEL* 31
D03 7
DMAReq1*
32
D04 8 IntSel* 33
D05 9 DMAck0* 34
D06 10 IOSEL* 35
D07 11 RESERVED 36
D08 12 A1 37
D09 13
DMAEnd*
38
D10 14 A2 39
D11 15 ERROR* 40
D12 16 A3 41
D13 17 INTReq0* 42
D14 18 A4 43
D15 19 INTReq1* 44
BS0* 20 A5 45
BS1* 21 STROBE* 46
-12V 22 A6 47
+12V 23 ACK* 48
+5V 24 RESERVED 49
GND 25 GND 50
Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
VME64x bus Connections for P1
Table 2.3 indicates the pin assignments for the VME64x bus
signals at the P1 connector. The P1 connector is the upper rear
connector on the AVME9675 board, as viewed from the front. The
connector consists of 32 rows of five pins labeled A, B, C, D and Z.
Pin Z1 is located at the upper right hand corner of the connector if
the board is viewed from the front component side.
Refer to the VME64x bus specification for additional information
on the VME64x bus signals.
TABLE 2.3: VME64x bus P1 CONNECTIONS
Pin Row Z Row A Row B Row C Row D
1
MPR
D00
BBSY*
D08
VPC
φ
2 GND D01
BCLR*
D09 GND
φ
3
MCLK
D02
ACFAIL*
D10
+V1
4 GND D03 BG0IN* D11
+V2
5
MSD
D04 BG0OUT* D12
RsvU
6 GND D05 BG1IN* D13
-V1
7
MMD
D06 BG1OUT* D14
-V2
8 GND D07 BG2IN* D15
RsvU
9
MCTL
GND BG2OUT* GND GAP*
10 GND SYSCLK BG3IN*
SYSFAIL*
GA0*
11
RESP*
GND BG3OUT*
BERR*
GA1*
12 GND DS1*
BR0*
SYSRESET*
+3.3V
13
RsvBus
DS0*
BR1*
LWORD* GA2*
14 GND WRITE*
BR2*
AM5
+3.3V
15
RsvBus
GND
BR3*
A23 GA3*
16 GND DTACK* AM0 A22
+3.3V
17
RsvBus
GND AM1 A21 GA4*
18 GND AS* AM2 A20
+3.3V
19
RsvBus
GND AM3 A19
RsvBus
20 GND IACK* GND A18
+3.3V
21
RsvBus
IACKIN*
SERA
A17
RsvBus
22 GND IACKOUT*
SERB
A16
+3.3V
23
RsvBus
AM4 GND A15
RsvBus
24 GND A07 IRQ7* A14
+3.3V
25
RsvBus
A06 IRQ6* A13
RsvBus
26 GND A05 IRQ5* A12
+3.3V
27
RsvBus
A04 IRQ4* A11
LI/I*
28 GND A03 IRQ3* A10
+3.3V
29
RsvBus
A02 IRQ2* A09
LI\O*
30 GND A01 IRQ1* A08
+3.3V
31
RsvBus
-12V
+5VSTDBY
+12V GND
φ
32 GND +5V +5V +5V
VPC
φ
Asterisk (*) is used to indicate an active-low signal.
Shaded area are pins defined under the VME64 bus specification.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
(
φ
) = Elongated (mate first, break last) connector contact.
VME64x bus Connections for P2
Table 2.4 indicates the pin assignments for the VME64x bus
signals at the P2 connector. The P2 connector is the lower rear
connector on the AVME9675 board, as viewed from the front. The
connector consists of 32 rows of five pins labeled A, B, C, D and Z.
Pin Z32 is located at the lower right hand corner of the connector if
the board is viewed from the front component side.
TABLE 2.4: VME64x bus P2 CONNECTIONS
Pin Row Z Row A Row B Row C Row D
1 C46 B41
Not Used
B42 C47
φ
2 GND B43
Not Used
B44 C48
φ
3 C49 B45
Not Used
B46 C50
4 GND B47
Not Used
B48 B1
5 B2 B49
Not Used
B50 B3
6 GND A1
Not Used
A2 B4
7 B5 A3
Not Used
A4 B6
8 GND A5
Not Used
A6 B7
9 B8 A7
Not Used
A8 B9
10 GND A9
Not Used
A10 B10
11 B11 A11
Not Used
A12 B12
12 GND A13
Not Used
A14 B13
13 B14 A15
Not Used
A16 B15
14 GND A17
Not Used
A18 B16
15 B17 A19
Not Used
A20 B18
16 GND A21
Not Used
A22 B19
17 B20 A23
Not Used
A24 B21
18 GND A25
Not Used
A26 B22
19 B23 A27
Not Used
A28 B24
20 GND A29
Not Used
A30 B25
21 B26 A31
Not Used
A32 B27
22 GND A33
Not Used
A34 B28
23 B29 A35
Not Used
A36 B30
24 GND A37
Not Used
A38 B31
25 B32 A39
Not Used
A40 B33
26 GND A41
Not Used
A42 B34
27 B35 A43
Not Used
A44 B36
28 GND A45
Not Used
A46 B37
29 B38 A47
Not Used
A48 B39
30 GND A49
Not Used
A50 B40
31
Not Used Not Used Not Used Not Used Not Used
φ
32 GND
Not Used Not Used Not Used Not Used
φ
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