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AP500/AP520/AP521 ACROPACK

USER

’S MANUAL

Acromag, Inc. Tel: 248-295-0310

- 28 - http://www.acromag.com

- 28 -

www.acromag.com

are not used on this module, this interrupt should always
be disabled.

4

1

0 = Disable Sleep Mode 1 = Enable Sleep Mode

The clock/oscillator circuit is disabled in sleep mode. The
UART will not lose the programmed bits when sleep mode
is activated or deactivated. The UART will not enter sleep
mode if any interrupts are pending.

5

1

0 = Disable the Receive Xoff Interrupt 1 = Enable the
Receive Xoff Interrupt

When software flow control in enabled, and one or two
sequential receive data characters match the
preprogrammed Xoff 1-2 values an interrupt will be issued.

6

1

0 = Disable RTS Interrupt 1 = Enable RTS Interrupt.

This Interrupt is generated when the RTS pin transitions
from a logic 0 to a logic 1. RTS is not output by this
module. Instead RTS is used to enable the transmitter of
the port. This interrupt should always be disabled.

7

1

0 = Disable CTS Interrupt 1 = Enable CTS Interrupt.

This interrupt will be issued when the CTS pin transitions
from a logic 0 to a logic 1. Since CTS is not used on this
module, this interrupt should always be disabled.

Bits 4 to 7 are only programmable when the EFR bit 4 is set to “1”. A power-
up or system reset sets all IER bits to 0 (bits 7-0 forced low).

3.2.6 ISR - Interrupt Status Register (READ Only)

The Interrupt Status Register is used to indicate that a prioritized interrupt is
pending and the type of interrupt that is pending. Six levels of prioritized
interrupts are provided to minimize software interaction. Performing a read
cycle on the ISR will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowledged until the
pending interrupt is serviced. Whenever the interrupt status register is
read, the interrupt status is cleared.  Note, only the current pending
interrupt is cleared by the read.  A lower level interrupt may be seen after
re-reading the interrupt status bits.

The following interrupt source table shows the data values (bit 0-5) for the
six prioritized interrupt levels and the interrupt sources associated with each
of these interrupts.

Table 3.7 Interrupt source

PRIORITY ISR BITS

Source of the Interrupt

«
...
27
28
29
30
31
...
»

Содержание AcroPack AP500

Страница 1: ...ion Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 2016 Acromag Inc Printed in the USA Data and specifications a...

Страница 2: ...ck Diagram 5 Figure 1 2 AP520 Block Diagram 5 Figure 1 3 AP521 Block Diagram 5 1 3 1 Ordering Information 6 Table 1 1 Ordering Options 6 1 3 2 Key Features 6 1 3 3 Key Features PCIe Interface 7 1 4 Si...

Страница 3: ...M Divisor Latch Registers Ports A H R W 25 Table 3 5 Baud Rate Divisors 14 7456MHZ 26 3 2 5 IER Interrupt Enable Register R W 27 Table 3 6 Interrupt Enable Register 27 3 2 6 ISR Interrupt Status Regis...

Страница 4: ...41 5 1 Physical 41 5 2 Power Requirements 41 Table 5 1 Model ID 41 5 3 Environmental Considerations 41 5 3 1 Operating Temperature 41 5 3 2 Other Environmental Requirements 42 5 3 2 1 Relative Humidi...

Страница 5: ...or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copy...

Страница 6: ...TS DTR DSR DCD and RI Figure 1 1 AP500 Block Diagram Exar 17V354 UART Mini PCIe Connector PCIe x1 RS 232 Transceivers 4 RS 232 Ports 4 Field I O Connector The AP520 uses the 16550 compatible Exar 17v3...

Страница 7: ...board provide up to 24 serial ports in a single VPX system slot or up to 16 serial ports in a PCIe system slot 16550 compatible Exar Quad or Octal UART with 16550 compatible register set 256 Byte FIF...

Страница 8: ...Windows applications interfacing with AcroPack modules VPX I O board products and PCIe I O Cards This software model APSW API WIN consists of low level drivers and Dynamic Link Libraries DLLs that ar...

Страница 9: ...ing resources regarding AcroPack modules are available for download on Acromag s website or by contacting your sales representative PCI Express MINI Card Electromechanical Specification REV 1 2 http w...

Страница 10: ...agnetic or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2...

Страница 11: ...above the maximum operating temperature 2 3 Board Configuration Power should be removed from the board when installing AP modules cables termination panels and field wiring Model AP500 520 UART commun...

Страница 12: ...RTS_A RXD _A 8 RSVD ISOL 7 RSVD ISOL 10 Field I O 5 5 3 TXD_A CTS_A RXD _A 9 Field I O 6 6 28 RTS_A GND GND 12 RSVD ISOL 11 RSVD ISOL 14 Field I O 7 7 4 RXD_A TXD_B TXD _B 13 Field I O 8 8 29 DSR_A R...

Страница 13: ...2 36 GND TXD_E TXD _E 44 RSVD ISOL 43 RSVD ISOL 46 Field I O 23 23 12 GND RXD_E TXD _E 45 Field I O 24 24 37 GND RTS_E RXD _E 48 RSVD ISOL 47 RSVD ISOL 50 Field I O 25 25 13 GND CTS_E RXD _E 49 Field...

Страница 14: ..._D RTS_H RXD _H 77 Field I O 40 40 45 RTS_D CTS_H RXD _H 80 RSVD ISOL 79 RSVD ISOL 82 Field I O 41 41 21 RXD_D GND GND 81 Field I O 42 42 46 DSR_D GND No Connect 84 RSVD ISOL 83 RSVD ISOL 86 Field I O...

Страница 15: ...L 10 Field I O 5 3 TXD_A CTS_A RXD _A 9 Field I O 6 37 28 RTS_A GND GND 12 RSVD ISOL 11 RSVD ISOL 14 Field I O 7 4 RXD_A TXD_B TXD _B 13 Field I O 8 38 DSR_A RXD_B TXD _B 16 RSVD ISOL 15 RSVD ISOL 18...

Страница 16: ...ISOL 43 RSVD ISOL 46 Field I O 23 12 GND RXD_E TXD _E 45 Field I O 24 46 GND RTS_E RXD _E 48 RSVD ISOL 47 RSVD ISOL 50 Field I O 25 13 GND CTS_E RXD _E 49 Field I O 26 47 GND GND GND 52 RSVD ISOL 51...

Страница 17: ...RTS_H RXD _H 77 Field I O 40 54 RTS_D CTS_H RXD _H 80 RSVD ISOL 79 RSVD ISOL 82 Field I O 41 21 RXD_D GND GND 81 Field I O 42 55 DSR_D GND No Connect 84 RSVD ISOL 83 RSVD ISOL 86 Field I O 43 22 DCD_...

Страница 18: ...ld I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by mul...

Страница 19: ...rted USB_D USB_D WAKE LED_WPAN LED_WLAN LED_WWAN W_DISABLE COEX1 COEX2 UIM_C4 UIM_C8 Note 2 UIM_PWR UIM_RESET UIM_CLK UIM_VPP UIM_DATA SIM card for cell signals may be available on some AcroPack carri...

Страница 20: ...e address and system interrupt request are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCIe bus configuration access is used to access...

Страница 21: ...figuration Registers Address Offset D31 D24 D23 D16 D15 D8 D7 D0 0x00 Device ID 0x0354 AP500 0x0358 AP520 521 Vendor ID 0x13A8 0x04 Status Command 0x08 Class Code 0x070002 Rev ID Current REV 0x0C BIST...

Страница 22: ...gisters See Table 3 4 0x0010 0x007F Reserved 0x0080 0x009A Device Configuration Registers See Table 3 3 0x009B 0x00FF Reserved Reserved 0x0100 0x01FF UART 0 FIFOs Read only 256 bytes of RX FIFO data 0...

Страница 23: ...3T 15 8 Read Write MPIO 15 8 output control Bits 15 8 0x00 0X098 MPIOINV 15 8 Read Write MPIO 15 8 input polarity select Bits 15 8 0x00 0x099 MPIOSEL 15 8 Read Write MPIO 15 8 select Bits 15 8 0xFF 0x...

Страница 24: ...REGISTERS THR AND RHR IN 8 BIT FORMAT The THR and RHR register address for channel 0 is shown in Table 3 4 below The THR and RHR for each channel 0 to 7 are located sequentially at address 0x0000 0x0...

Страница 25: ...ired Status for the receiver is provided via the Line Status Register LSR When a full character is received including parity and stop bits the data received indication bit bit 0 of the LSR is set to 1...

Страница 26: ...that at least one FIFO location is available The THR empty flag in the LSR register will be set to a logic 1 when at least one FIFO location is available 3 2 4 DLL DLM Divisor Latch Registers Ports A...

Страница 27: ...sampling each bit as near to the center of the bit time as possible To better understand the asynchronous timing used by this device note that the receive data line RxD is monitored for a high to low...

Страница 28: ...enabling the desired bits in the IER bit 3 of the Modem Control Register MCR must be set to a logic 1 to enable interrupts Table 3 6 Interrupt Enable Register IER BIT INTERRUPT ACTION 0 0 Disable Int...

Страница 29: ...ll be issued when the CTS pin transitions from a logic 0 to a logic 1 Since CTS is not used on this module this interrupt should always be disabled Bits 4 to 7 are only programmable when the EFR bit 4...

Страница 30: ...tate on the CTS or RTS signals Bits 6 and 7 are set when bit 0 of the FIFO Control Register is set to 1 A power up or system reset sets ISR bit 0 to logic 1 and bits 1 to 7 to logic 0 3 2 7 FCR FIFO C...

Страница 31: ...s the programmed trigger level One of four trigger levels can be selected bit 7 bit 6 Trigger Level 0 0 08 0 1 16 1 0 56 1 1 60 Bits 4 and 5 are only programmable when the EFR bit 4 is set to 1 A powe...

Страница 32: ...l output line TxD is forced to the space state low This bit acts only on the serial output and does not affect transmitter logic For example if the following sequence is used no invalid characters are...

Страница 33: ...RTS OUT1 and OUT2 do not have transmitter output paths Bit 3 of this register must be set to a logic 1 to enable the corresponding port to issue an interrupt Table 3 10 Modem Control Register MCR Bit...

Страница 34: ...re Table 3 11 Line Status Register LSR Bit FUNCTION PROGRAMMING 0 Data Ready DR 0 Not Ready reset low by CPU Read of RHR or FIFO 1 Data Ready set high when character received and transferred into the...

Страница 35: ...the FIFO and reflects the Break Interrupt when the break character is at the top of the FIFO It is detected by the host CPU during the first LSR read Only one 0 character is loaded into the FIFO when...

Страница 36: ...register when any one of these conditions are detected This interrupt is enabled by setting IER bit 2 to 1 A power up or system reset sets all LSR bits to 0 except bits 5 and 6 which are high 3 2 11 M...

Страница 37: ...or both the LSR MSR the setting of the status bits during a status register read operation is inhibited the status bit will not be set until the trailing edge of the read However if the same status co...

Страница 38: ...ed Feature Register EFR Xon 1 Xon 2 Xoff 1 Xoff 2 3 2 14 EFR Enhanced Feature Register Read Write The Enhanced Feature register is used to enable or disable enhanced features including software flow c...

Страница 39: ...SR bit 4 will be set to indicate detection of special character Bit 0 of the Xoff Xon registers corresponds with the LSB bit for the receive character When this feature is enabled the normal software...

Страница 40: ...smitter for output of the TxD signal The RTS signals do not have transmitter output paths on this model The CTS signals do not have a receiver input path on the AP521 model A power up or system reset...

Страница 41: ...ED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the documentation of your carrier board to...

Страница 42: ...ction cooled application with an AcroPack module will require purchase of the Heatsink AP CC 01 Table 5 1 Model ID Summarized below are the expected current draws for each of the specified power suppl...

Страница 43: ...10 500Hz 5G 2 Hours axis Vibration Random Operating Designed to comply with IEC 60068 2 64 10 500Hz 5G rms 2 Hours axis Shock Operating Designed to comply with IEC 60068 2 27 30G 11ms half sine 50G 3m...

Страница 44: ...rs using MIL HDBK 217F FN2 Per MIL HDBK 217 Ground Benign Controlled GBGC Temperature MTBF Hours MTBF Years Failure Rate FIT1 25 C 8 952 551 1 022 0 111 7 40 C 5 412 456 617 9 184 8 1 FIT is Failures...

Страница 45: ...Memory of whose contents are lost when power is removed Yes No Type SRAM SDRAM etc UART Internal Registers FIFOs SRAM Size 4k bytes AP500 8k bytes AP520 521 User Modifiable Yes No Function UART Commu...

Страница 46: ...ment is summarized in the table below Release Date DD MMM YYYY Version EGR DOC Description of Revision 27 APR 2016 A DWR ARP Initial Release 19 MAY 2016 B DWR ARP Corrected shock vibration specificati...

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