Acromag AcroPack AP500, Руководство пользователя

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AP500/AP520/AP521 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310 - 23 - http://www.acromag.com - 23 - www.acromag.com
The XR17V358 supports 32-bit Read and 32-bit Write transactions anywhere
in the mapped memory region (except reserved areas). In addition, to utilize
this feature fully, the device provides a separate memory location (apart
from the individual channel’s register set) where the RX and the TX FIFO can
be read from/written to, as shown in Table 3.2. The following is an extract
from the table showing the memory locations that support 32-bit
transactions:
The RX FIFO data can be read out 32-bits at a time at memory locations
0x100 (channel 0), 0x500 (channel 1), 0x900 (channel 2),......., 0x1D00
(channel 7). This operation is 4 times faster than reading the data in 256
separate 8-bit memory reads of RHR register (0x000 for channel 0, 0x400 for
channel 1, 0x800 for channel 2,......, 0x1C00 for channel 7).
The TX FIFO data can be loaded 32-bit (4 bytes) at a time at memory
locations 0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2),
............, 0x1900 (channel 6) and 0x1D00 (channel 7).
FIFO DATA LOADING AND UNLOADING THROUGH THE UART
CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 is shown in Table 3.4 below.
The THR and RHR for each channel 0 to 7 are located sequentially at address
0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0A000, 0x0C00 and 0x0E00.
Transmit data byte is loaded to the THR when writing to that address and
receive data is unloaded from the RHR register when reading that address.
Both THR and RHR registers are 16C550 compatible in 8-bit format, so each
bus operation can only write or read in bytes.
Table 3.4 UART Channel
Configuration Registers
Address Registers Read/Write Comments
0x0000 RHR- Receive Holding Register
THR- Transmit Holding Register
Read-only
Write-only
LCR[7]=0
0x0000 DLL - Divisor LSB Read/Write LCR[7]=1
0x0001 DLM - Divisor MSB Read/Write LCR[7]=1
0x0010 DLD - Divisor Fractional Read/Write LCR[7]=1
0x0001 IER -Interrupt Enable Register Read/Write LCR[7]=0
0x0010 ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR[7]=0
0x0011 LCR - Line Control Register Read/Write
0x0100 MCR - Modern Control Register Read/Write
0x0101 LSR - Line Status Register Read-only
0x0110 MSR - Modern Status Register
-Auto RS485 Delay
Read-only
Write-only
EFR bit-4= 1
0x0111 SPR- Scratch Pad Register Read/Write
ENHANCED REGISTER
0x1000 FCTR - Feature Control Register Read/Write