AP500/AP520/AP521 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
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www.acromag.com
3.2.3 THR - Transmitter Holding Register (WRITE Only)
The Transmitter Holding Register (THR) is a serial output data register that
shifts the data to the transmit data line (TxD). However, the THR data will
not pass to the TxD line unless the transceiver is first enabled. The
transceiver must be enabled to transmit data by setting bit-1 of the MCR
(Modem Control Register) to a logic “1”.
The Transmitter Holding Register (THR) is a serial port output data register
that holds from 5 to 8 bits of data, as specified by the character size
programmed in the Line Control Register. If less than 8 bits are transmitted,
then data is entered right-justified to the LSB. This data is framed as
required, then shifted to the transmit data line (TxD). In the idle state, TxD
is held high. In Loopback Mode, this data is looped back into the Receiver
Holding Register.
The status of the THR is provided in the Line Status Register (LSR). Writing
to the THR transfers the contents of the data bus (D7-D0) to the THR,
provided that at least one FIFO location is available. The THR empty flag in
the LSR register will be set to a logic 1 when at least one FIFO location is
available.
3.2.4 DLL & DLM - Divisor Latch Registers, Ports A-H (R/W)
The Divisor Latch Registers form the divisor used by the internal baud-rate
generator to divide the 14.7456MHz clock to produce an internal sampling
clock suitable for synchronization to the desired baud rate. The output of
the baud generator (RCLK) is sixteen times the baud rate. Two 8-bit divisor
latch registers per port are used to store the divisors in 16-bit binary format.
The DLL register stores the low-order byte of the divisor, DLM stores the
high-order byte. These registers must be loaded during initialization.
Note that bit 7 of the LCR register must first be set high to access the divisor
latch registers (DLL & DLM).
Upon loading either latch, a 16-bit baud counter is immediately loaded (this
prevents long counts on initial load). The clock may be divided by any
divisor from 1 to 2(16-1). The relationship between the baud rate, the
divisor, and the 14.7456MHz clock can be summarized in the following
equations:
MCRDIV)
x
Rate
Baud
x
(16
14.7456MHz
=
Divisor
MCRDIV)
Divisor x
x
(16
14.7456MHz
=
Rate
Baud
The MCRDIV term represents the state of bit-7 of the MCR (Mode Control
Register) as follows:
