Acromag 948 Series, Руководство пользователя

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AVME948x USER'S MANUAL Digital I/O Board
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Note that because inverted logic is used, a high level at the I/O
connector is read as a "0" in the Port Registers and a low level is
read as a "1". This is consistent with the use of open-collector
outputs to drive relays and switches. A logic "1" in the computer
produces a low level at the output driver to "pull in" a relay and turn
something "ON".
Reset Conditions: All of the I/O points are set to "0" which causes
the output drivers to go into an OFF (high impedance) state. The
result is that all I/O points are configured as inputs.
INTERRUPT BEHAVOIR
Several interrupt schemes are possible with the board's register
architecture. Some of the possibilities are:
•
Each point serviced by a separate software interrupt
handler routine.
•
A single software handler for the entire board.
•
A mix of some points causing interrupts, some polled.
Two different interrupt release methods are described in the
VME System Architecture. They are Release On Register Access
(RORA), and Release On Acknowledge (ROAK). The architecture
of this board follows the RORA method. This means that an
interrupt request is removed from the bus when the associated
interrupt point has been cleared. This method is necessary to allow
several interrupts to be serviced with a single handler, if so desired.
Interrupt Example
The following example outlines the steps taken to initialize the
board to cause interrupts.
1. Clear the global interrupt enable bit in the "Status/Control
Resister".
2. Write the interrupt level into the "Interrupt Level Register".
3. Write vector(s) into the "Vector Registers".
4. Write proper patterns to establish the interrupt level into the
Interrupt Input Polarity Register".
5. Write all 1's into the "Interrupt Clear Register " to reset interrupt
inputs.
6. Write 1's into the "Interrupt Enable Register" to enable individual
interrupts.
7. Write a 1 into the global interrupt enable bit of the
"Status/Control Register".
Interrupts may now occur from the board.
When the board asserts an interrupt, the following action takes
place:
1. The host processor asserts IACK* and a level of the interrupt it
is seeking, and if the level matches the board's, the board puts a
vector out on the data bus lines D0-D7. The original interrupt
request from the board remains asserted.
2. The host processor uses the vector to determine the software
interrupt handler to execute, and then executes it. For a single
handler per point scheme, the handler writes to the proper bit in
the "Interrupt Clear" register to remove the interrupt request.
This also clears its interrupt pending flag and interrupt input
flag. If other points have interrupts pending, another interrupt
request is asserted (or just remains) and upon returning from
the handler, another interrupt cycle is started.
3. If a software handler is used to handle several points, it could
service them at the same time that it services the original
interrupt by examining the "Interrupt Pending Register" to
determine what other interrupts need servicing.
Service of Interrupts
The following examples outline the steps necessary to service
an interrupt from the AVME948x.
Example A:
1. Disable the interrupt point(s) by writing a "zero" to the individual
bit(s) in the Interrupt Enable Register.
2. Clear the interrupt point(s) by writing a "one" to the individual
bit(s) in the Interrupt Pending/Clear Register.
3. Then reenable the interrupt point(s) by writing a "one" to the
individual bit(s) in the Interrupt Enable Register.
Example B:
1. Clear the Global Interrupt Enable bit in the Status Register.
2. Clear the Interrupt point(s) by writing a "one" to the individual
bit(s) in the Interrupt Pending/Clear Register.
3. Then reenable the Global Interrupt Enable bit in the Status
Register.
The interrupt input stimulus must be removed before the
interrupt can be cleared.
4.0 THEORY OF OPERATION
This section provides a functional description of the AVME948x
Digital I/O Board which consists of the following functional blocks:
•
VME address decode
•
VME control logic
•
Digital I/O map decode logic
•
Identification PROM
•
Status register
•
VME interrupter
•
Input comparators/buffers
•
Output latches/drivers
A block diagram is shown in Drawing 4500-741. Refer to the
Schematic and Parts Location Drawing 4500-737 for the items
referenced in the following information.
VMEbus INTERFACE
The VMEbus Interface logic contains the logic necessary to
interface the Digital I/O points to the VMEbus. This logic includes
VME address decode logic, the VME Control logic and the VME
Interrupter logic.
The VME Address Logic
The Digital I/O Board interfaces with the VMEbus as a non-
intelligent slave in the short I/O address space. The card will
recognize two of the Address Modifer Codes, the Short Supervisory
Access (2DH), and the Short Non-Supervisory Access (29H) codes.
Jumper J19 selects the Address Modifer Code that the card will
recognize. The starting address of the Digital I/O Board is
determined by jumpers on pins 1-12 of J17. This allows the Digital
I/O Board to reside in any one of the 64, 1K blocks of the short I/O
address space.
Integrated circuit U55 compares the VME address lines (A10 -
A15) and the Address Modifier line (AM2) to Jumpers J17 and J19.
If the two are equal, then the EQ* line is asserted. U57 checks the
remaining Address Modifier Lines and AS*, and then asserts the
CDEN* (card enable) line.
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