Acromag 948 Series, Руководство пользователя

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AVME948x USER'S MANUAL Digital I/O Board
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Table 2.3B: I/O Connectors P2 & P4
Functions P2 Pin # P4 Pin #
Port N+4, I/O Bit 7 C25 33
Bit 6 C26 35
Bit 5 C27 37
Bit 4 C28 39
Bit 3 C29 41
Bit 2 C30 43
Bit 1 C31 45
Bit 0 C32 47
Port N+5, I/O Bit 7 C17 34
Bit 6 C18 36
Bit 5 C19 38
Bit 4 C20 40
Bit 3 C21 42
Bit 2 C22 44
Bit 1 C23 46
Bit 0 C24 48
+5V C9 1,49
GND C15,C16 9,11
GND C13,C14 13,15
REF PORTS 4 & 5 C12 7
Pullup Ports 4 & 5 C11 5
Protect Ports 4 & 5 C10 3
Port N+6, I/O Bit 7 A8 17
Bit 6 A7 19
Bit 5 A6 21
Bit 4 A5 23
Bit 3 A4 25
Bit 2 A3 27
Bit 1 A2 29
Bit 0 A1 31
Port N+7, I/O Bit 7 A16 18
Bit 6 A15 20
Bit 5 A14 22
Bit 4 A13 24
Bit 3 A12 26
Bit 2 A11 28
Bit 1 A10 30
Bit 0 A9 32
+5V C1 2,50
GND C5,C6 10,12
GND C7,C8 14,16
REF Ports 6 & 7 C4 8
Pullup Ports 6 & 7 C3 6
Protect Ports 6 & 7 C2 4
BACKPLANE REQUIREMENTS
The AVME9480 is electrically and mechanically compatible with
the VMEbus Specification. The backplane connection is made
through the 96-pin DIN 41612 connector labeled P1. The signals
used are listed in Table 2.4.
Table 2.4: Backplane Connector P1
Pin
Number
Row A Signal
Mnemonic
Row B Signal
Mnemonic
Row C Signal
Mnemonic
1 D00 D08
2 D01 D09
3 D02 D10
4 D03 BG 0 IN* D11
5 D04 BG 0 OUT* D12
6 D05 BG 1 IN* D13
7 D06 BG 1 OUT* D14
8 D07 BG 2 IN* D15
9 GND BG 2 OUT* GND
10 SYSCLK BG 3 IN* SYSFAIL*
11 GND BG 3 OUT* BERR*
12 DS1* SYSRESET*
13 DSO* LWORD*
14 WRITE* AM5
15 GND
16 DTACK* AM0
17 GND AM1
18 AS* AM2
19 GND AM3
20 IACK* GND
21 IACKIN*
22 IACKOUT*
23 AM4 GND A15
24 A07 IRQ7* A14
25 A06 IRQ6* A13
26 A05 IRQ5* A12
27 A04 IRQ4* A11
28 A03 IRQ3* A10
29 A02 IRQ2* A09
30 A01 IRQ1* A08
31
32
+5V +5V +5V
USE WITH SOLID-STATE RELAYS
The AVME984X Digital I/O Board may interface with industry
standard Solid-State relays and termination panels PB16A, PB32,
and their equivalents.
Configuring The AVME948x
On Model AVME948x, the following jumpers or shorting clips
should be in place: J1,J2,J3,J4,J5,J6,J7 and J8. Pullup resistor
networks R57, R50, R56, R51, R35, R52, R54, and R53 are
optional.
Table 2.5 lists the Module Number Bit Positioning for the I/O
port registers.
Table 2.5 Module Number Bit Positioning
I/O Port
Number
Module Number
7 6 5 4 3 2 1 0 PB16A
Connected To
N+0 7 6 5 4 3 2 1 0 P3
N+1
15 14 13 12 11 10 9 8
P3
N+2 7 6 5 4 3 2 1 0 P3
N+3
15 14 13 12 11 10 9 8
P3
N+4 7 6 5 4 3 2 1 0 P4
N+5
15 14 13 12 11 10 9 8
P4
N+6 7 6 5 4 3 2 1 0 P4
N+7
15 14 13 12 11 10 9 8
P4
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