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AVME948x USER'S MANUAL Digital I/O Board
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VME Interrupter

The VME Interrupter is made up of a series of registers that

control the eight I/O interrupt points and the interrupt mode. Refer to
the Interrupter Block Diagram (Drawing 4500-740) and the memory
map (Table 3.1) for items referenced in the following discussion.

The VME interrupter on the Digital I/O card is a Release On

Register Access (RORA) type interrupter and will return an eight bit
vector during the interrupt acknowledge cycle. The RORA type
interrupter will release the interrupt request line (IRQx*) after the
interrupt has been cleared. The interrupter logic contains a
programmable interrupt level accessible through the Interrupt Level
Register.

The eight I/O interrupt points are level sensitive and prioritized.

Interrupt point 7 has the highest priority and interrupt point 0 has the
lowest priority. Each I/O interrupting point may be programmed with
its own interrupt vector. Further, each I/O interrupt point may be
individually masked and the interrupt polarity selected. Refer to the
following paragraphs for further discussion of the interrupt registers.

Interrupt Pending/Clear Register (Read/Write, 80)

The Interrupt Pending Register reflects the status of the eight

I/O interrupt points from I/O Port 0. A "1" in a bit position indicates
an interrupt is pending for the corresponding point. Each bit is the
logical AND of its associated "Interrupt Enable" and "Interrupt Input"
bits. Hence, an input that is not enabled will never have its interrupt
pending bit set to a "1".

An individual interrupt can be cleared by writing a "1" to its bit

position if the input level has been negated. If the input level has not
been negated, then the individual point must be masked or the
interrupt level must be changed in the "Interrupt Input Polarity
Register", and then a 1 written to its bit position in the "Interrupt
Pending/Clear Register". This is the only way to clear interrupts
from the board. This is known as the "Release on Register Access"
(RORA) method as defined in the VME System Architecture.

Interrupt Pending/Clear Register for I/O Port 0 Inputs

MSB

LSB

Point

Reset Condition: All interrupts cleared.

Interrupt Inputs Register (Read, 82)

The Interrupt Inputs Register provides the status of the eight I/O

interrupt points prior to the point where they are masked by the
"Interrupt Enable" register. This allows the level detecting circuitry
for some inputs to be used in a polled or non-interrupt mode, while
others operate in an interrupt mode. A "1" in a bit position indicates
the input went through the transition defined by the "Interrupt Input
Polarity Register". A write to the corresponding "Interrupt Clear
Register" bit will clear the interrupt input flag if the input level has
been negated. If the input level has not been negated, then the
interrupt input flag will remain set.

Interrupt Inputs Register for I/O Port 0 Inputs

MSB

LSB

Point

Reset Condition: All interrupt inputs cleared unless the interrupt
condition is still present.

Interrupt Enable Register (Read/Write, 83)

The Interrupt Enable Register provides a mask bit for each of

the eight I/O interrupt points. A "0" in a bit position will prevent the
corresponding I/O interrupt point from causing an interrupt. A "1"
will allow the input to cause an interrupt (providing the global
interrupt enable bit is set).

Interrupt Enable Register for I/O Port 0 Inputs

MSB

LSB

Point

Reset Condition: All interrupt points masked.

Interrupt Level Register (Read/Write, 84)

The Interrupt Level Register maintains the interrupt level (1-7)

that the board responds with when it issues an interrupt request to
the VMEbus.

Reset Condition: Register unaffected.

Interrupt Input Polarity Register (Read/Write, 85)

The Interrupt Input Polarity Register determines the level that

will cause an interrupt for each of the eight I/O interrupt points. A
"1" in a bit position means that an interrupt will occur when the I/O
interrupt point is high. A "0" in a bit position means that an interrupt
will occur when the I/O interrupt point is low.

Interrupt Input Polarity Register for I/O Port 0 Inputs

MSB

LSB

Point

Reset Condition: All inputs will cause interrupts when I/O Interrupt
Point is low.

Interrupt Vector Registers (Read/Write, Odd-Bytes from 86-95)

The Interrupt Vector Registers maintain the interrupt vectors for

each of the eight I/O interrupt lines. This allows each I/O interrupt
line to be serviced by its own software handler. A single software
handler can be used by simply making all of the vectors the same.
In this case, the handler will have to determine the interrupting point
by examining the "Interrupt Pending Register".

Reset Condition: Registers unaffected.

Digital I/O Port Registers (Read/Write, 100-107)

The I/O Port Registers reflect and/or control the state of the

bidirectional I/O points. Points are grouped 8 to a port. To use a
point as an input, first write a 0 to it to cause the output driver to go
into an OFF (high impedance) state. That lets the point be pulled to
a high voltage level by an onboard pull-up resistor. The point may
then be driven by an external device. Reading the point will reflect
the INVERTED level at the I/O connector. To use a point as an
output, write the desired "1" or "0" to the point. If the point is read, it
will reflect the state of the output as well.

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