Acorn BBC Master 128, Руководство по обслуживанию

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Master Series Service Manual
2 Check all connections from the CPU address bus (IC14 pins 9 to 20
and pins 22 to 25 inclusive) to the DRAM address multiplexers (ICs 29
30 and 33, see circuit diagram for pin numbers). Then check the
voltage levels of these signals at the multiplexer input pins. All
signals should have good CMOS levels (less than 1V for 0, greater than
3V for 1). A constant 0 or 5V level implies a short to the relevant
power rail. Poor logic levels imply shorting to another logic signal.
3 Check that the address at the DRAM inputs is stable for at least
15ns after RAS goes low and changes no later than 50ns after that
edge, see figure 8. This should occur once for every active high
period of the system 2MHz clock out of the VIDPROC and once for every
active low period.
4 Check that the noise around logic LOW signals is generally less than
500mV. If it is not, then some signals may be shorting or a decoupling
capacitor may be missing.
5 Check that the data bus is properly connected between the CPU and
the DRAMs.
7.1.12 You can type but get two or more copies around the screen.
1 Check Test Points TP7 to TP20 (the CRTC scanning outputs, shown on
circuit diagram to the left of the CRTC IC22) to make sure that the
correct addresses are being generated. Any line stuck high or low or
shorting to another pin will give strange screen effects.
Note: MA13 IC22 pin 17 is used to switch the address multiplexing
circuits between modes 7/135 and any other modes. This line should be
static in any given mode.
2 Check that all of the lines from the CRTC IC22 to the CRTC
Multiplexer IC31 actually get there.
3 Check that the lines CO and Cl from the 74LS259 (IC10 pins 4 and 5)
to the CRTC Multiplexer (IC31 pins 38 and 39) are properly connected
and change at least once if you switch between modes.
4 Check that the lines from the CRTC/MUX IC31 to the DRAMs are correct
with no short or open circuits.
7.2 Sideways RAM
1 Check all connections to the memory address multiplexers.
2 Check RAS and CAS at the DRAMs, see figure 8.
3 Check that the two links LK18 and LK19 are in the correct position
for your use.
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