Acorn BBC Master 128, Руководство по обслуживанию

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Master Series Service Manual
System VIA:- A 6522 allows several sources to create maskable
interrupts. The sources are:-
a) CRTC vertical synchronisation.
b) A-D converter; end of conversion signal.
c) CRTC light pen strobe.
d) Keyboard key detect.
It also provides the previously mentioned slow data bus.
Port B on this device generates and reads a number of internal
hardware strobes. These are as follows:-
Port B Data Strobe Active Level
Note: Q is the value of D after the port write operation is completed
2MHz Internal I/0:- Only one internal I/O component operates at this
speed, the internal second processor TUBE. Its data bus is connected
directly to the CPU data bus.
The second processor interface will only be specified as a hardware
data transfer definition. In this way, the actual second processor
used will not be constrained by this specification.
This is a parallel port providing the following data access signals:-
i) DO to D7 .... A bi-directional bus to TTL levels. ii) AO to A2 ...
. A uni-directional bus to CMOS levels.
The following control and timing signals are provided:-
i) Host CPU phi2 .... CMOS levels
ii) System Reset .... TTL levels
iii) Host CPU nIRQ .... This must be an 'open collector' node
with an active low TTL level
iv) 8MHz timing reference.... TTL levels
v) TUBE chip select .... CMOS levels
vi) Read/Write .... TTL levels
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