Acer Altos R310, Руководство по обслуживанию

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53 Altos R310
BIOS POST Checkpoint Codes
The POST code checkpoints are references and instructions used duing the BIOS pre-boot process.
The following table describles the checkpoints and associated beep codes, if any, that may occur during
the POST portion of the BIOS.
Checkpoint Code Beep Code Description
01h One short beep
before boot
02h Verify Real Mode. If the CPU is in protected mode,
turn on A20 and pulse the reset line, forcing a
shutdown 0.
NOTE: Hook routine should not alter DX, which
holds the powerup CPUID.
03h Disable Non-Makable Interrupts (NMI).
04h Get CPU type from CPU registers and other
methods.
Save CPU type in NVRAM.
NOTE: Hook routine should not alter DX, which
holds the powerup CPUID.
06h Initialize system hardware. Reset the DMA
controllers, disable video, clear any pending
interrupts from the real-time clock and setup port B
register.
07h Disable system ROM shadow and start to execute
ROMEXEC code from the flash part. This taks is
pulled into the build only when the ROMEXEC
relocatoin is installed.
08h Initialize chipset registers to the lnitial POST Values.
09h Set in-POST flag in CMOS that indicates we are in
POST. If this bit is not cleared by post -
ClearBootFlag(AEh), the BIOS no next boot
determines that the current configuration caused
POST to fail and uses default values for
configuration.
Clear the CMOS diagnostic byte (register E). Check
the real-time clock and verify the battery has not lost
power. Checksum the CMOS and verify it has not
been corrupted.
0Ah Initialize CPU registers.
0Bh Enable CPU cache. Set bits in CMOS related to
cache.
0Ch Set the initial POST values of the cache registers if
not integrated into the chipset.
0Eh Set the initial POST values of registers in the
integrated I/O chip.
0Fh Enable the local bus IDE as primary or secondary
depending on other drives detected.
10h Initialize power management
11h General dispatcher for alternate register initialization.
Set initial POST values for other hardward devices
defined in the register tables.