Acer Altos R310, Руководство по обслуживанию

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Chapter 4 54
12h Restore the contents of the CPU control word
whenever the CPU is reset.
13h Early reset of PCI devices required to disable bus
master. Assumes the presence of a stack and
running from decompressed shadow memory.
14h Verify that the 8742 keyboard controller is
responding. Send a self-test command to the 8742
and wait for results. Also read the switch inputs from
the 8742 and write the keyboard controller command
byte.
16h 1-2-2-3 Verify that the ROM BIOS checksum to zero.
17h Initialize external cache before autosizing memory.
18h Initialize all three of the 8254 timers. Set the clock
timer (0) to binary count, mode 3 (square wave
mode), and read/write LSB then MSB. Initialize the
clock timer to zero. Set the RAM refresh timer (1) to
binary count, mode 2
1Ah Initialize DMA command register with these settings:
1. Memory to memory disabled
2. Channel 0 hold address disabled
3. Controller enabled
4. Normal timing
5. Fixed priority
6. Late write selection
7. DREQ sense active
8. DACK sense active low
Initialize all 8 DMA channels with these settings:
1. Single mode
2. Address increment
3. Auto initialization disabled (channel 4 - Cascade)
4. Verify transfer
1Ch Initialize interrupt controllers for some shut-downs.
20h 1-3-1-1 Verify that DRAM refresh is operating by polling the
refresh bit in PORTB.
22h 1-3-1-3 Reset the keyboard.
24h Set segment-register addressibility to 4 GB.
28h 1-3-3-1 Using the table of configurations supplied by the
specific chipset module, test each DRAM
configuration to see if that particular configuration is
valid. Then program the chipset to its autosized
configuration.
Before autosizing, disable all caches and all shadow
RAM.
29h 1-3-3-2 Initialize the POST Memory Manager.
2Ah Zero the first 512K of RAM.
2Ch 1-3-4-1 Test 512K base address lines.
2Eh 1-3-4-3 Test first 512K of RAM.
2Fh Initialize external cache before shadowing.
32h Compute CPU speed.
Checkpoint Code Beep Code Description