Abov MC96F8104M, Руководство пользователя

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MC96F8204 ABOV Semiconductor Co., Ltd.
11.8.13 Register Map
Name Address Direction Default Description
USTCR1 D9H R/W 00H USART Control Register 1
USTCR2 DAH R/W 00H USART Control Register 2
USTCR3 DBH R/W 00H USART Control Register 3
USTST DCH R/W 80H USART Status Register
USTBD DDH R/W FFH USART Baud Rate Generation Register
USTDR DEH R/W 00H USART Data Register
Table 11.12
USART Register Map
11.8.14 USART Register Description
USART module consists of USART baud rate generation register (USTBD), USART data register (USTDR), USART
control register 1 (USTCR1), USART control register 2 (USTCR2), USART control register 3 (USTCR3), and USART
status register (USTST).
11.8.15 Register Description for USART
USTBD (USART Baud Rate Generation Register) : DDH
7 6 5 4 3 2 1 0
USTBD7 USTBD6 USTBD5 USTBD4 USTBD3 USTBD2 USTBD1 USTBD0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
USTBD [7:0] The value in this register is used to generate internal baud rate in UART mode or to
generate SCK clock in SPI mode. To prevent malfunction, do not write
‘0’ in UART
mode and do not write
‘0’ or ‘1’ in synchronous or SPI mode.
USTDR (USART Data Register) : DEH
7 6 5 4 3 2 1 0
USTDR7 USTDR6 USTDR5 USTDR4 USTDR3 USTDR2 USTDR1 USTDR0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : 00H
USTDR [7:0] The USART Transmit buffer and Receive buffer share the same I/O address with this
DATA register. The Transmit Data Buffer is the destination for data written to the
USTDR register. Reading the USTDR register returns the contents of the Receive
Buffer. Write to this register only when the DRE flag is set. In SPI master mode, the
SCK clock is generated when data are written to this register.