57
MC96F8204
ABOV Semiconductor Co., Ltd.
9
I/O Ports
9.1
I/O Ports
The MC96F8204 has three groups of I/O ports (P0~P2). Each can be easily configured by software as I/O pin, internal
pull up and open-drain pin to meet various system configurations and design requirements. Also P0 include function
that can generate interrupt according to change of state of the pin.
9.2
Port Register
9.2.1
Data Register (Px)
Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to the
corresponding bit of the Px. If ports are configured as input ports, the data can be read from the corresponding bit of
the Px.
9.2.2
Direction Register (PxIO)
Each I/O pin can be independently used as an input or an output through the PxIO register. Bits cleared in this register
will make the corresponding pin of Px to input mode. Set bits of this register will make the pin to output mode. Almost
bits are cleared by a system reset, but some bits are set by a system reset.
9.2.3
Pull-up Resistor Selection Register (PxPU)
The on-chip pull-up resistor can be connected to I/O ports individually with a pull-up resistor selection register (PxPU).
The pull-up register selection controls the pull-up resister enable/disable of each port. When the corresponding bit is 1,
the pull-up resister of the pin is enabled. When 0, the pull-up resister is disabled. All bits are cleared by a system reset.
9.2.4
Open-drain Selection Register (PxOD)
There are internally open-drain selection registers (PxOD) for P0. The open-drain selection register controls the open-
drain enable/disable of each port. Almost ports become push-pull by a system reset, but some ports become open-
drain by a system reset.
9.2.5
De-bounce Enable Register (P0DB)
P0[4:0] support debounce function. Debounce clocks of each ports are fx/1, fx/4, fx/32, and fx/4096.
9.2.6
Port Function Selection Register (P0FSRH, P0FSRM, P0FSRL, P1FSR)
These registers define alternative functions of ports. Please remember that these registers should be set properly for
alternative port function. A reset clears the P0FSRH, P0FSRM, P0FSRL, P1FSR register to
‘00H’, which makes all
pins to normal I/O ports.
Содержание MC96F8104M
Страница 13: ...13 MC96F8204 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 20 Pin SOP Package...
Страница 14: ...14 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 2 20 Pin TSSOP Package...
Страница 15: ...15 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 3 16 Pin SOPN Package...
Страница 16: ...16 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 4 10 Pin SSOP Package...
Страница 17: ...17 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 5 8 Pin SOP Package...
