Abov MC96F6332D, Руководство пользователя

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MC96F6432
June 22, 2018 Ver. 2.9 149
11.7.6.1 Timer/Counter 2 Register Description
The timer/counter 2 register consists of timer 2 A data high register (T2ADRH), timer 2 A data low register
(T2ADRL), timer 2 B data high register (T2BDRH), timer 2 B data low register (T2BDRL), timer 2 control High
register (T2CRH) and timer 2 control low register (T2CRL).
11.7.6.2 Register Description for Timer/Counter 2
T2ADRH (Timer 2 A data High Register) : C5H
7 6 5 4 3 2 1 0
T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
T2ADRH[7:0]
T2 A Data High Byte
T2ADRL (Timer 2 A Data Low Register) : C4H
7 6 5 4 3 2 1 0
T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
T2ADRL[7:0] T2 A Data Low Byte
NOTE) Do not write
“0000H” in the T2ADRH/T2ADRL register when
PPG mode.
T2BDRH (Timer 2 B Data High Register) : C7H
7 6 5 4 3 2 1 0
T2BDRH7 T2BDRH6 T2BDRH5 T2BDRH4 T2BDRH3 T2BDRH2 T2BDRH1 T2BDRH0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
T2BDRH[7:0] T2 B Data High Byte
T2BDRL (Timer 2 B Data Low Register) : C6H
7 6 5 4 3 2 1 0
T2BDRL7 T2BDRL6 T2BDRL5 T2BDRL4 T2BDRL3 T2BDRL2 T2BDRL1 T2BDRL0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
T2BDRL[7:0] T2 B Data Low Byte