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3-16
Chapter 3
VL6
DRAM Bank Interleave:
Four options are available: Auto
'
Disabled
'
2-Way
'
4-Way. The default setting is
Auto
. Depending on your SDRAM module structure, the 4-Way setting can make the
performance best. If you choose the wrong setting, the computer system will not run in a
stable manner. For detailed information on your SDRAM module, please ask your SDRAM
module manufacturer.
Delay DRAM Read Latch:
Five options are available: Auto
'
No Delay
'
0.5ns
'
1.0ns
'
1.5ns. The default
setting is Auto. This option can increase the DRAM signal strength to give you better
compatibility for DRAM modules.
SDRAM Cycle Length:
Two options are available: 2 or 3. This option sets the CAS latency timing. of the DRAM
system memory access cycle when SDRAM system memory is installed on the motherboard.
The default setting is
3
.
DRAM Clock:
Two options are available: Host CLK or 66 MHz. The default setting is Host CLK. This
option is used to set the working speed of SDRAM same as CPU working frequency, or keep
it at 66 MHz.
Memory Hole:
Two options are available: Disabled or 15M - 16M. The default setting is
Disabled
. This
option is used to free up the memory block 15M-16M. Some special peripherals need to use
a memory block located between 15M and 16M, and this memory block has a size of 1M.
We recommend that you disable this option.
Read Around Write
Two options are available: Disabled or Enabled. The default setting is
Disabled
. This item is
designed for DRAM optimization feature. If a memory read is addressed to a location whose
latest write is being held in a buffer before being written to memory, the read is satisfied
through the buffer contents, and the read is not sent to the DRAM
Concurrent PCI/Host
Two options are available: Disabled or Enabled. The default setting is
Disabled
. When
disable, CPU bus will be occupied during the entire PCI operation period.
System BIOS Cacheable:
Two options are available: Disabled or Enabled. The default setting is
Disabled
. When you
select Enabled, you get faster system BIOS executing speed via the L2 cache.
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