Abit KD7-B, Руководство пользователя

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BIOS Setup 3-15
AGP Master 1 WS Write:
Two options are available: Disabled Enabled. The default setting is Disabled . This implements a
single delay when writing to the AGP Bus. When you set it to Enabled , two-wait states are used by the
system, allowing for greater stability.
AGP Master 1 WS Read:
Two options are available: Disabled Enabled. The default setting is Disabled . This implements a
single delay when reading to the AGP Bus. When you set it to Enabled , two-wait states are used by the
system, allowing for greater stability.
DBI Output for AGP Trans.:
Two options are available: Disabled Enabled. The default setting is Disabled . In order to mitigate the
effects of simultaneous switching outputs, AGP 3.0 adopts a scheme called
D
ynamic
B
us
I
nversion (DBI)
to limit the maximum number of simultaneous transitions on source synchronous data transfers.
NOTE:
This item only shows up when you installed the display adapter that supports AGP 3.0
specifications.
Back to Advanced Chipset Features Setup Menu:
CPU & PCI Bus Control:
Press <Enter> key to enter the CPU & PCI Bus Control menu.
PCI Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled . When Enabled, writes to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to
Disabled , the system will wait one state before data is written to the PCI bus.
PCI Master 0 WS Read:
Two options are available: Enabled or Disabled. The default setting is Enabled . When Enabled, reads to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to
Disabled , the system will wait one state before data is written to the PCI bus.
User’s Manual