Publication No. PEX430-0HH/1QD
Functional Description 21
4.1.3
PCI Express Switch
The PCI Express (PCIe) switch function is performed by a PLX PEX8532. This device
provides 2.5 Gbps per lane (5 Gbps per lane full duplex) of aggregated bandwidth.
The non-blocking internal crossbar architecture supports full wire speed, and
provides a maximum payload size of 256 Bytes.
On the PEX430 the PEX8532 has 16 lanes connected to the VPX connector, 8 lanes
connected to the XMC connector and 4 lanes connected to the PCIe to PCI/PCIX
bridge. The 16 lanes connected to the VPX connector can be configured in several
different ways as described earlier. One of the PEX8532 ports connected to the VPX
connector can be configured for Non-Transparent mode. The setting of the PEX430
with a non-transparent switch port requires the use of configuration data stored in
the associated EEPROM. All the ports connected to the VPX connector support lane
reversal, and also support auto-width negotiation enabling the PEX430 to be
connected to systems supporting lower lane widths.
It should be noted that if the PEX430 is connected so that for example two 4 lane
ports are connected to a single 8 lane device the link may fail to negotiate. In this
case the PEX430 should be reconfigured to present an 8 lane port or the second 4 lane
port should be physically disconnected.
4.1.4
PCI Express to PCI/PCIX Bridge
The PCIe to PCI/PCIX bridge function is performed by a PLX PEX8114. The PEX8114
interfaces to the PCIe bus (via the PCIe switch) with up to 4 PCIe lanes, allowing a
maximum 2.5 Gbps per lane bit rate. The other side of the bridge is either PCI or
PCIX supporting a 32 bit or a 64-bit wide data path running at up to 133 MHz; giving
bandwidths up to 8 Gbps.
The PEX430 supports the use of the PEX8114 in forward bridge mode. In this mode
configuration accesses are sent from the PCI Express root complex.
The PEX8114 can operate in Transparent or Non-transparent mode. In Non-
Transparent mode the bridge isolates the processor domains on each side. Data
transfers between domains occurs using address translation. In Non-Transparent
mode configuration accesses occur on both the PCI/PCIX bus and the PCIe port.
There are two ‘hosts’ in this configuration and each can access or send data to
devices on both sides of the bridge. Each host has its own memory map for the
devices to which it has access. The setting of the PEX430 with a non-transparent
bridge port requires the use of configuration data stored in the associated EEPROM.
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