Aaeon SBC-400, Руководство пользователя

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18 SBC-400 User's Manual
3. Carefully pull the SIMM out of the socket with your fingers.
4. Repeat the above steps for each module you remove.
Selecting cache memory size
The SBC-400 features a 2nd level memory cache that supports
128, 256, or 512 KB of cache memory. Higher cache memory can
improve your system's performance.
The cache uses SRAM chips in three sizes: 32 KB, 64 KB and 128
KB. The on-board cache memory banks consists of four SRAM
chip sockets, each of which accepts one "Tag" chip. All SRAM
chips must have a speed of 20 ns or faster. The table below shows
the possible cache configurations:
Cache Configuration
Cache size Tag RAM Data RAM
128 KB one 32 K x 8 four 32 KB x 8 SRAMs
256 KB one 32 K x 8 four 64 KB x 8 SRAMs
512 KB one 32 K x 8 four 128 K x 8 SRAMs
Cache memory select (JP1)
When the cache size changes, you must make sure that JP1 is set to
match the new cache memory size. The following chart shows the
proper jumper setting for each cache configuration:
Cache memory select (JP1)
128 KB 256 KB 512 KB
1 2
3 4
1 2
3 4
1 2
3 4