4. IDE Interface
27
Alternate Status Register
(3F6h, Read - 8 bits)
The alternate status register contains the same information as does the status register
at 1F7h. The only difference is that reading this register does not clear the interrupt,
which implies interrupt acknowledgment of the interrupt source. All bit definitions are the
same. See the following figure, "Alternate Status Register".
7
6
5
4
3
2
1
0
Data Request
Drive Seek Complete
Error
Corrected Data
Index
Drive Write Fault
CORR IDX
ERR
DRQ
DSC
DWF
DRDY
BSY
Drive Ready
Busy
Alternate Status Register
Digital Output Register
(3F6h, Write - 8 bits)
This register contains two control bits as shown in the following figure, "Digital Output
Register".
7
6
5
4
3
2
1
0
Interrupt Enable
SRST IEN
-
Software Reset
-
-
-
-
-
Digital Output Register
IEN—Interrupt Enable
This bit enables the interrupt from the disk drive when set to a logical 0. Setting this bit
to a logical 1 will three-state the interrupt.
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