4. IDE Interface
24
Status Register
(1F7h, Read - 8 bits)
This register contains the drive/controller status. The contents of this register are
updated at the completion of each command. If the BSY bit is active no other bits are
valid. When the BSY bit is not set (logical 0) the remaining bits in the status register are
valid.
When an interrupt is pending the drive considers that the host has acknowledged the
interrupt when it reads the status register. The bits in this register are defined in the
following figure, "Status Register".
BSY—Busy
The BSY bit is active whenever the drive accesses the IDE registers. This locks out the
host from accessing the registers. This bit is activated under the following conditions:
•
After a hard reset (as opposed to CNTRL-ALT-DEL), or at the activation of the
software reset through the digital output register.
•
After the host writes to the command register with a read, read long, read buffer,
seek recall, initialize drive parameters, verify, identify, or diagnostic command.
•
After the transfer of 512 bytes of data during the execution of a write, format track, or
write buffer command, or when 512 bytes of data and four ECC bytes have been
transferred during the execution of a write long command. When BSY is active
(logical 1), any host read of the command block register will return the status
register. The host may not write any command blocks when BSY is active.
7
6
5
4
3
2
1
0
Data Request
Drive Seek Complete
Error
Corrected Data
Index
Drive Write Fault
CORR IDX
ERR
DRQ
DSC
DWF
DRDY
BSY
Drive Ready
Busy
Status Register
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