4. IDE Interface
28
SRST—Software Reset
This bit, when set, will hold the drive in reset until cleared. If two drives are daisy
chained, both will be reset simultaneously.
Drive Address Register
(3F7h, Read - 8 bits)
This register loops back the drive select and head select addresses of the currently
selected drive. The bits in this register are shown in the following figure, "Drive Address
Register".
7
6
5
4
3
2
1
0
Write Gate
Drive Select
HS2
HS1
HS0
HS3
DS0
WTG
RSVD
Reserved
DS1
Head Select Address
(1©s Complement)
Drive Address Register
RSVD—Reserved
This bit is reserved for floppy disk drive subsystem usage. In the original AT
implementation the hard disk and floppy disk systems shared this register location. The
ZT 8952 does not drive this bit on the STD bus in order to avoid contention should a
floppy disk controller be in the system.
WTG—Write Gate
This bit is set when a write to the hard disk is in process.
HS3 - HS0—Head Select Address
These bits represent the 1's complement of the binary coded address of the currently
selected head. For example, head 3 (0011) selected is represented by 1100, which is
the 1's complement of 3 in binary.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
