3. Operational Overview
16
STD BUS COMPATIBILITY
The ZT 8952 is compatible with Version 1.2 of the
STD 32 Bus Specification, a superset
of the STD-80 Series Bus Specification.
CPU AND STD BUS INTERFACE
The ZT 8952 interfaces two standards, the IDE interface and the STD bus. In addition to
signal reformatting, ZT 8952 also performs byte packing and unpacking for 8-bit CPUs
when transferring to and from the 16-bit only IDE interface. A state machine handles
this transfer in dynamic fashion. In 16-bit STD 32 card cages ZT 8952 will perform 16-bit
data transfers directly to and from the IDE drive and the STD 32 bus. 16-bit transfers
allow a maximum data transfer rate of 4 Mbytes/second, assuming four clocks per
transfer, or 3.2 Mbytes/second with five clocks per transfer.
Data Transfers
The ZT 8952 performs both 8-bit and 16-bit transfers as defined by the host processor.
All transfers are eight bits except to I/O address 1F0h, which causes the ZT 8952 to
drive the signal IO16* low. This informs the CPU that a 16-bit transfer is desired. If the
CPU is a 16-bit processor such as the ZT 8901, and the system is an STD 32 system,
the processor will drive BHE* low. This indicates to ZT 8952 that a high data byte is
being transferred during this cycle.
For 8-bit processors or for 16-bit processors used in older 8-bit backplanes it is
recommended that W2 be removed so that BHE* is not used. BHE* was formerly a
STD-80 signal called MEMEX that was not clearly defined. Some processors either
drive this signal low or allow it to be driven via a parallel port bit. Since ZT 8952
interprets this signal for data size, an 8-bit transfer would be misinterpreted as a 16-bit
transfer should BHE* be driven low. W2 should be installed when the ZT 8952 is used in
an STD 32 backplane with a 16-bit processor. W2 may be left installed when used with
an 8-bit processor that always drives BHE* (the old MEMEX signal) high.
MEMORY
The ZT 8952 does not occupy any part of the memory map.
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