Chapter 3. STD Bus Interface
26
Non-Maskable Interrupts
The ZT 8905 supports the STD 32 signal NMIRQ* for system errors (see the "Non-Maskable
Interrupt Structure" illustration below). The NMIRQ* signal is maskable through port 61h, bit 3. Write
a 0 to enable, or a 1 to disable HMI for bit 3 of port 61h.
SYSTEM
CHIPSETS
PENTIUM
STD BUS
NMIRQ*
PORT
61h
BIT 3
0 = Enable
1 = Disable
SOFTWARE
MASK
NMI
Non-Maskable Interrupt Structure
RESET
The ZT 8905 is automatically reset with a precision voltage monitoring circuit that detects when Vcc
is below the acceptable operating limit of 4.75 V. In addition, the on-board 3.3 V power supply is
monitored and will reset the ZT 8905 when below 3.0 V. Other sources of reset include the watchdog
timer, local pushbutton switch, and the STD bus pushbutton reset signal, PBRESET* (P48).
The ZT 8905 responds to any of these reset sources by initializing local peripherals and driving the
STD bus system reset, SYSRESET* (P47). Refer to the section on "Multiple Master Reset" in this
chapter for further details about that environment.
MULTIPLE MASTER AND INTELLIGENT I/O
Ziatech offers two architectures for increasing the number of microprocessors in a single system:
multiple master and intelligent I/O. Applications can use multiple master, intelligent I/O, or a
combination of the two.
The following topics discuss multiple master, intelligent I/O, multiple master vs. intelligent I/O,
multiple master system requirements, and reset.
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