Chapter 1. Introduction
2
STD 32 Single Master
The ZT 8905 supports additional memory and I/O through the STD 32 bus. Both Standard
Architecture (8- and 16-bit) and Extended Architecture (8-, 16-, and 32-bit) transfer types are
dynamically supported through the STD 32 interface. Jumperless configuration of interrupt, DMA, and
STD 32 bus memory and I/O space is configured through the BIOS SETUP utility. See the section
"ZT 8905 SETUP" in Chapter 2 for more information.
STD 32 Multiple Master (STAR SYSTEM)
The ZT 8905 is configurable to operate in a multiple master architecture as a Permanent Master or a
Temporary Master. With this architecture, up to seven ZT 8905 boards share STD bus memory and
I/O resources. The Permanent Master provides the system clock and reset function and also
provides the pull-up signals for the open-collector signals on the STD 32 bus. The Permanent Master
is also responsible for initializing shared memory and other system I/O on behalf of any Temporary
Masters. The STAR BIOS manages all of the system initialization.
FEATURES OF THE ZT 8905
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STD 32 bus compatible
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PCI compatible local bus (CompactPCI compliant)
•
Single and multiple master operation
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Pentium processor CPUs to 200 MHz
•
Numeric coprocessor support (Pentium)
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16 Kbytes of CPU cache (expandable with L2 cache)
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Optional IDE hard disk interface (local to ZT 8905)
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8, 16, 32, or 48 Mbytes of DRAM memory
•
2 Mbytes of Flash memory (expandable to 4 Mbytes)
•
Optional 32-bit PCI local bus peripheral support (through CompactPCI)
--Super VGA (640x480x16M through 1280x1024x64K)
--Contact Ziatech for additional peripherals
•
Standard AT® peripherals include:
--Two enhanced interrupt controllers (8259)
--Three counter/timers (one 8254)
--Real-time clock/CMOS RAM (146818)
--Two enhanced DMA controllers (8237)
--8042 compatible keyboard controller
•
Centronics printer port (ECP/EPP compatible)
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Two 16C550 RS-232 serial ports
•
Single stage watchdog timer
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Speaker interface
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