Index
xxi
modem status register (serial controller)
Serial Controller
Serial Controller Registers, Modem Status Register............................................................... 67
multi-I/O cable ZT 90205 (illus.)
Specifications
Cable, Illus--ZT 90205 Multi-I/O Cable .................................................................................. 104
multi-I/O connector (J5)
Board Configuration
Cuttable Trace Descriptions, CT1/CT2 (Frontplane DMA)...................................................... 89
DMA Controller
DMA Controller, ZT 8905 Specifics ......................................................................................... 47
Interrupt Controller
Interrupt Sources ..................................................................................................................... 33
Introduction
Functional Blocks, IEEE 1284 Parallel Port Interface ............................................................... 8
J5 Multi-I/O Connector Illustration ............................................................................................. 8
Serial Controller
ZT 8905 Specifics.................................................................................................................... 61
Specifications
Mechanical, Connectors, J5 (Multi-I/O Connector) ............................................................... 101
multi-I/O Connector (J5)ZT 90205 multi-I/O cable
Serial Controller
Serial Channel Interface .......................................................................................................... 62
multiple latch control register illustration
Counter/Timers
Counter/Timer Multiple Latch Control Register ....................................................................... 45
multiple master architecture
Introduction
Product Definition, STD 32 Mult Master (STAR SYSTEM) ....................................................... 2
STD 32 Bus Interface
Multiple Master and Intelligent I/O, Intro.................................................................................. 26
Multiple Master System Requirements.................................................................................... 28
Multiple Master and Intelligent I/O, Multiple Master................................................................. 27
Multiple Master and Intelligent I/O, Reset................................................................................ 30
Multiple Master Vs. Intelligent I/O............................................................................................ 28
Multiple Master Architecture (illus.)
STD 32 Bus Interface
Multiple Master, Illus.--Mult Master Architecture ..................................................................... 27
multiprocessing
STD 32 Bus Interface
STD 32 Bus Compatibility, Multiprocessing............................................................................. 23
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