Z3 Technology HE4K-DCK-10 Hardware Specification Download Page 4 | Manualshive

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HE4K-DCK-10

HARDWARE SPECIFICATION

CONFIDENTIAL

DOC-USR-0100-01

____________________________________________________________________________________

Z3 Technology, LLC

♦

100 N. 8th St. STE 250

♦

Lincoln, NE 68508-1369 USA

♦

+1.402.323.0702

LIST OF FIGURES

Figure 1: HE4K-DCK-10 Front Dimensions ................................................................................. 6

Figure 2: HE4K-DCK-10 Physical Block Diagram (Chassis & Camera Not Included) .................................. 8

Figure 3: HE4K-DCK-10 Block Diagram .................................................................................... 9

Figure 4: Correct KEL Ribbon Cable Wiring Diagram ................................................................... 11

Figure 5: Interface Front End PCB Hardware Layout .................................................................. 13

Figure 6: Layout of the I/O Jack and PoE PCB Production Version .................................................. 24

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Summary of Contents for HE4K-DCK-10

Page 1: ...fidential information of Z3 Technology LLC Z3 This document may not be used reproduced disclosed or disseminated to anyone without the prior written approval of an authorized representative of Z3 Z3 T...

Page 2: ...00 01 ____________________________________________________________________________________ Z3 Technology LLC 100 N 8th St STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 Revision History Version Date...

Page 3: ...y LLC 100 N 8th St STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 TABLE OF CONTENTS GENERAL DESCRIPTION 6 1 0 FEATURES 7 2 0 PHYSICAL 8 3 0 THERMAL CONSIDERATIONS 10 4 0 CONNECTING THE HE4K DCK 10 T...

Page 4: ...E 250 Lincoln NE 68508 1369 USA 1 402 323 0702 LIST OF FIGURES Figure 1 HE4K DCK 10 Front Dimensions 6 Figure 2 HE4K DCK 10 Physical Block Diagram Chassis Camera Not Included 8 Figure 3 HE4K DCK 10 Bl...

Page 5: ...PCB J2 Pin Out 15 Table 5 IFE PCB J3 Pin Out 15 Table 6 IFE PCB J4 Pin Out 17 Table 7 IFE PCB J5 Pin Out 17 Table 8 IFE PCB J6 Pin Out 18 Table 9 Main Encoder PCB J1 Pin Out 19 Table 10 Main Encoder...

Page 6: ...1 0 The HE4K DCK 10 is an H 265 HEVC H 264 and MJPEG video encoder designed to be a companion to the Sony FCB ER8300 4K block camera It is capable of accepting 4K UHD video from the camera at 30 frame...

Page 7: ...69 USA 1 402 323 0702 FEATURES 2 0 Direct connection to the Sony FCB ER8300 block camera IP Video encoder supports H 265 HEVC and H 264 at 4K 3840x2160 30 fps Supports RTP RTSP RTCP and UDP Optional O...

Page 8: ...s the CPU and is the core of the encoder This PCB also includes a Micro SD card socket Some versions of the Main Encoder PCB also contain a 2 5mm circular jack used to access the CPU console port usef...

Page 9: ...0 01 ____________________________________________________________________________________ Z3 Technology LLC 100 N 8th St STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 Figure 3 shows a block diagram...

Page 10: ...p Location Max Tj Notes CPU U3 Main Encoder PCB 105 C The chip spec is not very clear and lists some contradicting values such as max TJ of 125 C and max ambient temperature of 70 C FPGA U7 Front End...

Page 11: ...1 connected to pin 1 and another is a cross type with pin 1 connected to pin N N 30 in this case Z3 Technology provides the correct cable as part of the HE4K DCK RPS Please ONLY USE THE CABLE PROVIDED...

Page 12: ...5V 12V 16V If no ER8300 camera attached with USB device Power over Ethernet PoE 48V 802 3af at class 0 Power Consumption 4W Full power encode and stream H 265 4K at 30fps on Gb Ethernet Video Input ER...

Page 13: ...DCK 10 camera dock video encoder system 7 1 Interface Front End PCB The Interface Front End PCB converts the video format provided by the FCB ER8300 or a Micro HDMI jack to LVDS as required by the en...

Page 14: ...t on the Sony FCB ER8300 camera Pin J1 Pin ER8300 Signal Notes 1 30 DC Input Power from encoder to camera Power comes directly from DC input jack or PoE module whichever is active 2 29 3 28 4 27 5 26...

Page 15: ...Utility 12 Clock 3 Data2 13 Gnd 4 Gnd 14 Clock 5 Data2 15 CEC 6 Data1 16 GND 7 Gnd 17 DDC_CLK 8 Data1 18 DDC_DAT 9 Data0 19 5V 10 Gnd Table 4 IFE PCB J2 Pin Out 7 1 3 J3 FPGA JTAG J3 is a debug connec...

Page 16: ...G_CCLK 13 GND 14 FPGA_CONFIG_DIN 15 MIPI0_D3M 16 N C MIPI0_D3P 18 FPGA_CONFIG_INITB 19 GND 20 FPGA_CONFIG_PROGB 21 MIPI0_CKM 22 GND 23 MIPI0_CKP 24 N C 25 GND 26 N C 27 MIPI0_D2M 28 GND 29 MIPI0_D2P 3...

Page 17: ...st be removed to disconnect the internal power supply from J5 and J1 When using internal power from the I O Jack PCB R9 must be populated with a 0 Ohm resistor and J5 must be left unconnected J5 is no...

Page 18: ...Technology LLC 100 N 8th St STE 250 Lincoln NE 68508 1369 USA 1 402 323 0702 9 DEB_D11 FPGA pin H3 10 DEB_D10 FPGA pin J4 11 DEB_D9 FPGA pin H1 12 DEB_D8 FPGA pin K5 13 DEB_D7 FPGA pin J1 14 DEB_D6 F...

Page 19: ...e 7 2 1 J1 JTAG Connector Pin Signal Pin Signal 1 TMS 2 TRST 3 TDI 4 GND 5 3 3V power 6 Key N C 7 TDO 8 GND 9 TCK 10 GND 11 RTCK optional 12 GND 13 EMU0 optional 14 EMU1 optional Table 9 Main Encoder...

Page 20: ...I2_D3M 66 N C 67 GND 68 N C 69 MIPI2_D1P 70 UART2_TXD 71 MIPI2_D1M 72 UART2_RXD 73 GND 74 GND 75 MIPI2_CKP 76 I2S_LRCLK IR_CUT_0_CONTROL1 GPIO0_7 77 MIPI2_CKM 78 I2S_SCLK IR_CUT_0_CONTROL2 GPIO0_5 79...

Page 21: ...presence of an RS 232 level serial port interface used for the console Pin Signal 1 GND 2 MDI_0 3 MDI_0 4 MDI_1 5 MDI_1 6 MDI_2 7 MDI_2 8 MDI_3 9 MDI_3 10 GND 11 LED1_LINK PHY_AD1 12 LED0_ACTIV PHY_AD...

Page 22: ...the Sony FCB ER8300 block camera This header mates with J28 on the I O Jacks PCB Pins Signal 1 2 3 12V input from jack or PoE to Main Encoder PCB 4 3 3V output from Main Encoder PCB 5 6 7 8 GND Table...

Page 23: ...68508 1369 USA 1 402 323 0702 7 2 7 J30 Analog Audio I O This header contains the input and output analog audio signals It is intended to provide a path for a differential microphone input and one si...

Page 24: ...op yellow and bottom blue layout of the I O Jack and PoE board Figure 6 Layout of the I O Jack and PoE PCB Production Version The headers on the bottom side mate with the headers on the Main Encoder P...

Page 25: ...ack for 12V power entry J21 RCA jack Composite video output J29 3 5mm stereo jack Microphone input Tip MIC_N Ring MIC_P Ring GND J32 2 5mm stereo jack Serial port interface RS232 level Tip RX Ring TX...

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