Yamaha V9938 Programmer'S Manual Download Page 1

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V9938 MSX-VIDEO

Technical Data Book

Programmer’s Guide

ASCII CORPORATION / NIPPON GAKKI CO., LTD.

NIPPON GAKKI CO., LTD.

Page 1 of 108

Summary of Contents for V9938

Page 1: ...V9938 MSX VIDEO TechnicalDataBook Programmer sGuide ASCII CORPORATION NIPPON GAKKI CO LTD NIPPON GAKKI CO LTD 1985 ASCII CORP NIPPON GAKKI CO Page 1 of 108 2010 2015 Eugeny Brychkov ...

Page 2: ... 1985 ASCII CORP NIPPON GAKKI CO Page 2 of 108 2010 2015 Eugeny Brychkov This page is intentionally left blank ...

Page 3: ...nd hardware compatibility was taken in further developments on the IT market V9938 is one of the most popular video processors in the family of Texas Instruments original chips improved by a group of companies from Japan and US Its follower V9958 was a VDP chip for limited release of MSX2 and MSX Turbo R machines and the last VDP in the family V9990 can only be found in add on cartridges The book ...

Page 4: ... 1985 ASCII CORP NIPPON GAKKI CO Page 4 of 108 2010 2015 Eugeny Brychkov This page is intentionally left blank ...

Page 5: ...he V9938 Full bit mapped mode 80 column text display Access using X and Y coordinates for easier programming the X Y coordinates are independent of the screen mode Fundamental hardware commands to decrease the processing time and reduce programming complexity Digitize and external synchronization Color palette 9 bits x 16 patterns Linear RGB video output More sprites per horizontal line Because th...

Page 6: ... 1985 ASCII CORP NIPPON GAKKI CO Page 6 of 108 2010 2015 Eugeny Brychkov This page is intentionally left blank ...

Page 7: ... 2 1 4 Display registers 20 2 1 5 Access registers 21 2 1 6 Command registers 22 2 2 Status registers 0 to 9 23 3 SCREEN MODES 25 3 1 TEXT1 mode 25 3 2 TEXT2 mode 29 3 3 MULTICOLOR MC mode 34 3 4 GRAPHIC1 G1 mode 38 3 5 GRAPHIC2 G2 and GRAPHIC3 G3 modes 42 3 6 GRAPHIC4 G4 mode 47 3 7 GRAPHIC5 G5 mode 50 3 8 GRAPHIC6 G6 mode 55 3 9 GRAPHIC7 G7 mode 59 4 COMMANDS 63 4 1 Types of Commands 63 4 2 Page...

Page 8: ...4 4 12 POINT 92 4 5 Speeding up the processing of commands 93 4 6 States of the registers after command execution 94 5 SPRITES 95 5 1 Sprite mode 1 G1 G2 MC 96 5 2 Sprite mode 2 G3 G4 G5 G6 G7 100 5 3 Special rules for sprite color settings 107 6 SPECIAL FUNCTIONS 108 6 1 Alternate display of two graphics screen pages 108 6 2 Displaying two graphics screens at 60Hz 108 6 3 Interlace display 108 ...

Page 9: ...eir sprite pattern generator table overlap In some circumstances such behavior may be changed in favor or mixing sprite colors to have pseudo multi colored sprites Color A property of the pixel on the screen Color of the pixel may come from various sources from global color register from pattern color table or from sprite color table Colors can also be coded in the palette registers through setup ...

Page 10: ...to set its pattern but also put its pattern number into the layout map VDP when displaying the picture reads the number of pattern to display and then refers to its actual image to font pattern generator table Port Is a physical latch with specific system address for CPU reads and writes to communicate with VDP VDP has four ports port 0 is a read write data port port 1 is write register set up por...

Page 11: ...is a set of memory cells used by VDP to keep information about picture displayed on the screen VRAM is accessed for picture displaying purposes as well as for picture modifications Picture displaying occurs continuously when VDP is enabled V9938 may have 16K to 128K VRAM and depending on the memory organization and size may not be able to function properly in specific modes See description of regi...

Page 12: ... 1985 ASCII CORP NIPPON GAKKI CO Page 12 of 108 2010 2015 Eugeny Brychkov This page is intentionally left blank ...

Page 13: ...nterrupt routine which can write to or read from VDP port s and thus break the proper sequence In case of Z80 CPU use DI disable interrupts at the start and EI enable interrupts at the end of VDP your access code Data byte is written first bits D0 D7 and register number is written next to data byte bits R0 R5 If interrupt involving VDP operations will occur between these two operations it may caus...

Page 14: ...lette address pointer and subsequently write two bytes of data in specific order into port 2 Every color consists of 3 sets of 3 bits red green and blue component value 0 7 Note after writing pair of data to port 2 palette register number pointer in register R 16 auto increments MSB 7 6 5 4 3 2 1 0 LSB Register 16 0 0 0 0 C3 C2 C1 C0 Palette Port 2 first byte 0 R2 R1 R0 0 B2 B1 B0 Data 1 Red data ...

Page 15: ...he address counter A16 to A14 3 Set the address counter A7 to A0 4 Set the address counter A13 to A8 and specify if following data command will be read or write 5 Read or write data to the memory Step 1 Switching banks VRAM to expansion RAM Applications are used to work with Video RAM thus re specification of the bank is rarely necessary It will be required if your application will need to access ...

Page 16: ...y important as if you specify that next operation will be a read VDP will pre fetch value from the memory specified by the address set up earlier and will get ready for CPU data read If you will not do so and issue read command VDP may not get enough timeslot to read data from the VRAM and CPU may get invalid data If you specify that next command will be a write then VDP does not do pre fetch and ...

Page 17: ...ormed IE0 Enables interrupt from vertical retrace M1 Screen mode flag see Screen Modes chapter M2 Screen mode flag see Screen Modes chapter SI Sprite size when set to 1 sprite size is 16 16 If set to 0 sprite size is 8 8 R 1 MAG Sprite enlarging If set to 1 sprites are enlarged double size MS Mouse when set to 1 sets the color bus into input mode and enables mouse If set to 1 sets color bus into o...

Page 18: ...When displaying information on the screen VDP uses color pattern sprite and other information from video RAM It is important to set proper starting addresses of such VRAM locations by writing to specified table base address registers Note you should ensure that unused bits are set to 0 Further in the book bit set to 0 will mean that this bit has to be set to 0 1 will mean that this bit has to be s...

Page 19: ...ister R 7 are displayed alternatively blinked MSB 7 6 5 4 3 2 1 0 LSB R 13 ON3 ON2 ON1 ON0 OF3 OF2 OF1 OF0 Display time for even page Display time for odd page Blinking period register In the TEXT2 mode and in bit map modes of GRAPHIC4 to GRAPHIC7 two pages can be alternatively displayed blinked Write to this register R 13 in order for blinking to start MSB 7 6 5 4 3 2 1 0 LSB R 20 0 0 0 0 0 0 0 0...

Page 20: ...tical screen size can be 192 or 212 depending on LN bit of register R 9 Setting R 23 to value other than 0 may display un initialized parts of the memory which may look as garbage Display of virtual screen is performed in cycle meaning that when increasing value of R 23 top of virtual screen appears at the bottom of visible screen Please see pictures below Original screen in GRAPHIC1 mode Offset s...

Page 21: ... 14 0 0 0 0 0 A16 A15 A14 VRAM access base register R 14 contains three senior bits of VRAM access address In all modes except GRAPHIC1 GRAPHIC2 MULTICOLOR and TEXT1 if there s a carry flag from A13 the value in this register is automatically incremented MSB 7 6 5 4 3 2 1 0 LSB R 15 0 0 0 0 S3 S2 S1 S0 Status register pointer R 15 points to the respective status register S 0 S 9 to be read MSB 7 6...

Page 22: ... 7 6 5 4 3 2 1 0 LSB R 36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Destination X low register R 37 0 0 0 0 0 0 0 DX8 Destination X high register R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 Destination Y low register R 39 0 0 0 0 0 0 DY9 DY8 Destination Y high register MSB 7 6 5 4 3 2 1 0 LSB R 40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 Number of dots X low register R 41 0 0 0 0 0 0 0 NX8 Number of dots X high register R ...

Page 23: ... button of mouse was pressed This flag is not reset when reading status register S 1 in both set ups 5 1 ID The identification number of the VDP chip 0 FH Horizontal scan interrupt flag Is set if VDP scans line specified in register R 19 If IE1 is set interrupt is generated FH is reset when S 1 is read MSB 7 6 5 4 3 2 1 0 LSB S 2 TR VR HR BD 1 1 EO CE Status register 2 7 TR Transfer ready flag If ...

Page 24: ...rmation about collision location of the sprites or location of light pen or relative movement of the mouse MSB 7 6 5 4 3 2 1 0 LSB S 7 C7 C6 C5 C4 C3 C2 C1 C0 Color register This color register is used when executing commands POINT and VRAM to CPU and contains VRAM data MSB 7 6 5 4 3 2 1 0 LSB S 8 BX7 BX6 BX5 BX4 BX3 BX2 BX1 BX0 Coded color X register low S 9 1 1 1 1 1 1 1 BX8 Coded color X regist...

Page 25: ...area per screen 4K bytes Controls Pattern font VRAM pattern generator table Screen pattern location VRAM pattern name table Pattern color code 1 High order four bits of R 7 Pattern color code 0 Low order four bits of R 7 Background color code Low order four bits of R 7 Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 0 0 0 0 1 MSX system default values BASIC SCREEN number Pattern generator ...

Page 26: ...ont displayed on the screen for each pattern is constructed from 8 bytes with 6 high order bits displayed and 2 low order bits not displayed Pattern generator table base is stored in the register R 4 Example of pattern generator table is provided below MSB LSB Offset 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 Pattern number o PN0 8 9 10 11 12 13 14 15 Pattern number 1 PN1 2040 2041 2042 2043 2044 2045 2046 2...

Page 27: ...er R 2 and corresponds to the cell 0 0 with address 0 in the picture below Columns 0 1 2 3 39 X 0 0 1 2 3 39 1 40 41 42 43 79 22 880 881 882 919 23 920 921 922 959 Rows Y 3 1 4 Color register settings Color settings are located in the register R 7 Bits TC3 TC0 specify pattern color code of the pixels identified as 1 in the bitmap values of pattern generator table bits BD3 BD0 specify pattern color...

Page 28: ...A10 MSB 7 6 5 4 3 00800h 00FFFh Pattern generator table 0 2 1 0 LSB R 4 0 0 0 0 0 0 0 1 A16 A15 A14 A13 A12 A11 MSB 7 6 5 4 3 01000h 2 1 0 LSB R 2 0 0 0 0 0 013BFh Pattern layout table 1 1 0 0 A16 A15 A14 A13 A12 A11 A10 MSB 7 6 5 4 3 01800h 01FFFh Pattern generator table 1 2 1 0 LSB R 4 0 0 0 0 0 0 1 1 A16 A15 A14 A13 A12 A11 Maximum of 32 pages may be allocated in the same manner if VDP has 128K...

Page 29: ...tern location VRAM pattern name table Pattern color code 1 High order four bits of R 7 Pattern color code 0 Low order four bits of R 7 Background color code Low order four bits of R 7 Blinking pattern color code 1 High order four bits of R 12 Blinking pattern color code 0 Low order four bits of R 12 Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 0 1 0 0 1 Other flags LN bit of R 9 0 24 li...

Page 30: ...ell 0 0 with address 0 in the picture below Note that if LN bit of R 9 is set to 1 then 26 lines are displayed plus an upper half of 27th pattern line is displayed MSB 7 6 5 4 3 2 1 0 LSB R 2 0 A16 A15 A14 A13 A12 1 1 Pattern layout table Screen mapping of pattern layout table is provided below Columns 0 1 2 3 79 X 0 0 1 2 3 79 1 80 81 82 83 159 25 2000 2001 2002 2079 26 2080 2081 2082 2159 Rows Y...

Page 31: ...alues of pattern generator table bits BD3 BD0 specify pattern color code of the pixels identified as 0 in the bitmap values of pattern generator table as well as screen border color Alternate blinking color is set in R 12 Note screen border color is the same as the pattern backdrop color in TEXT2 mode 3 2 6 Blink register settings Color codes set in registers R 7 and R 12 will be alternately displ...

Page 32: ...ded in the table below Delay data binary Time ms Delay data binary Time ms 0 0 0 0 0 1 0 0 0 1335 1 0 0 0 1 166 9 1 0 0 1 1509 9 0 0 1 0 333 8 1 0 1 0 1668 8 0 0 1 1 500 6 1 0 1 1 1835 7 0 1 0 0 667 5 1 1 0 0 2002 6 0 1 0 1 834 4 1 1 0 1 2169 5 0 1 1 0 1001 3 1 1 1 0 2336 3 0 1 1 1 1168 2 1 1 1 1 2503 2 ...

Page 33: ...0h Pattern generator table 0 MSB 7 6 5 4 3 2 1 0 LSB R 10 0 0 0 0 0 0 0 0 A16 A15 A14 01800h MSB 7 6 5 4 3 2 1 0 LSB R 4 0 0 0 0 0 0 1 0 02000h 1985 ASCII CORP NIPPON GAKKI CO Page 33 of 108 2010 2015 Eugeny Brychkov A16 A15 A14 A13 A12 A11 Pattern layout table 1 02870h 02A00h 02B0Eh Color table 1 03000h Pattern generator table 1 03800h 04000h 1FFFFh Maximum of 16 pages may be allocated in the sam...

Page 34: ...es Controls Color block color code VRAM pattern generator table Color block location VRAM pattern name table Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 0 0 0 1 0 MSX system default values BASIC SCREEN number Pattern generator Pattern layout Sprite patterns Sprite attributes 3...

Page 35: ...r code D Color of the pattern when y 0 4 8 12 16 or 20 Pattern name n E F Color code E Color code F G H Color code G Color code H Color of the pattern when y 1 5 9 13 17 or 21 I J Color code I Color code J K L Color code K Color code L Color of the pattern when y 2 6 10 14 18 or 22 M N Color code M Color code N Color of the pattern when y 3 7 11 15 19 or 23 O P Color code O Color code P Start of t...

Page 36: ...er settings You can set color of the margin of the screen backdrop color specifying BD3 BD0 bits in register R 7 Note that bits TC3 TC0 of R 7 are ignored 3 3 4 Sprite settings Set the start address of the sprite attribute table in registers R 5 and R 11 set start address of the sprite pattern generator table in register R 6 For details about sprites please refer to section Sprite mode 1 ...

Page 37: ...0h 00400h 00700h Pattern layout table 0 00700h Sprite attribute table 0 00780h 00800h 01000h Pattern generator table 0 Maximum of 32 pages may be allocated in the same manner if VDP has 128K bytes attached to it 1FFFFh 1985 ASCII CORP NIPPON GAKKI CO Page 37 of 108 2010 2015 Eugeny Brychkov ...

Page 38: ...RAM pattern generator table Screen pattern location VRAM pattern name table Pattern color codes 1 0 Specified as a group for each 8 bit pattern in color table Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 0 0 0 0 0 MSX system default values BASIC SCREEN number Pattern generator ...

Page 39: ...tor table base is stored in the register R 4 Example of pattern generator table is provided below MSB LSB Offset 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 Pattern number o PN0 8 9 10 11 12 13 14 15 Pattern number 1 PN1 2040 2042 2043 2044 2045 2046 2047 Pattern number 255 PN255 3 4 2 Pattern layout table settings The pattern layout table is a map of the screen per screen image Every byte location of the scr...

Page 40: ...s is set in registers R 3 and R 10 MSB 7 6 5 4 3 2 1 0 LSB R 3 A13 A12 A11 A10 A9 A8 A7 A6 R 10 0 0 0 0 0 A16 A15 A14 Color table base address registers Color table size is 32 bytes each byte organized in the same way as register R 7 FC is foreground color BC is background color Patterns 0 7 are assigned the first color from color table patterns 8 15 are assigned second color from the color table ...

Page 41: ...efer to section Sprite mode 1 3 4 6 Example of VRAM allocation for GRAPHIC1 mode 00000h 00400h Sprite generator table 0 00400h Pattern layout table 0 00700h 00700h Sprite attribute table 0 00780h 00800h 1985 ASCII CORP NIPPON GAKKI CO Page 41 of 108 2010 2015 Eugeny Brychkov Maximum of 32 pages may be allocated in the same manner if VDP has 128K bytes attached to it 01000h Pattern generator table ...

Page 42: ...nt VRAM pattern generator table Screen pattern location VRAM pattern name table Pattern color codes 1 0 Specified in pattern color table for 8 pixel groups Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags GRAPHIC2 Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 0 0 1 0 0 Mode flags GRAPHIC3 Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1...

Page 43: ... 1 0 2 0 3 0 31 0 1 0 1 1 1 2 1 3 1 31 1 0 7 1 7 2 7 31 7 Upper of the screen 0 8 1 8 2 8 31 8 0 15 1 15 2 15 31 15 Middle of the screen 0 16 1 16 2 16 31 16 22 0 22 1 22 2 22 31 22 23 0 23 1 23 2 23 31 23 Lower of the screen Rows Y Pattern generator table Pattern color table base address 00000h 007FFh Pattern images for upper of the screen 256 Pattern colors for upper of the screen 256 00800h 00F...

Page 44: ...e location This table has three 32 8 locations upper middle and lower arranged consecutively where defined patterns can be displayed Pattern layout table base address is stored in register R 2 and corresponds to the cell 0 0 with address 0 in the picture below Example of pattern generator table is provided below Color table identifies color 1 upper four bits and color 0 lower four bits for every r...

Page 45: ... 6 5 4 3 2 1 0 LSB R 3 A13 1 1 1 1 1 1 1 R 10 0 0 0 0 0 A16 A15 A14 Color table base address registers 3 5 4 Color register settings You can set color of the margin of the screen backdrop color specifying BD3 BD0 bits in register R 7 Note that bits TC3 TC0 of R 7 are ignored 3 5 5 Sprite settings Set the start address of the sprite attribute table in registers R 5 and R 11 set start address of the...

Page 46: ... to it 00FFFh Pattern generator table middle 01000h GRAPHIC2 mode GRAPHIC3 mode 017FFh Pattern generator table lower 02000h 027FFh Pattern color table upper 02800h 02FFFh Pattern color table middle 03000h 037FFh Pattern color table lower 03800h 03AFFh Pattern layout table 04000h 1FFFFh 01800h Sprite pattern table 01800h 01BFFh Sprite pattern table 01BFFh 01C00h Sprite attribute table Sprite color ...

Page 47: ...f 512 per screen Sprite mode Sprite mode 2 VRAM area per screen 32K bytes Controls Graphics VRAM pattern name table Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 0 1 1 0 0 MSX system default values BASIC SCREEN number Pattern layout bitmap Sprite patterns Sprite attributes Sprit...

Page 48: ...6 5 4 3 2 1 0 LSB 0 Color code for 0 0 Color code for 1 0 Base address 1 Color code for 2 0 Color code for 3 0 127 Color code for 254 0 Color code for 255 0 128 Color code for 0 1 Color code for 1 1 27134 Color code for 252 211 Color code for 253 211 27135 Color code for 254 211 Color code for 255 211 Pattern layout table base address is stored in register R 2 and corresponds to the cell 0 0 in th...

Page 49: ... Eugeny Brychkov R 5 A14 A13 A12 A11 A10 1 1 1 Sprite attribute table low R 11 0 0 0 0 0 0 A16 A15 Sprite attribute table high R 6 0 0 A16 A15 A14 A13 A12 A11 Sprite pattern generator table 3 6 4 Example of VRAM allocation for GRAPHIC4 mode 00000h Pattern name table 07000h Sprite pattern table 07800h Sprite color table Maximum of 4 pages may be allocated in the same manner if VDP has 128K bytes at...

Page 50: ...f 512 per screen Sprite mode Sprite mode 2 VRAM area per screen 32K bytes Controls Graphics VRAM pattern name table Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 1 0 0 0 0 MSX system default values BASIC SCREEN number Pattern layout bitmap Sprite patterns Sprite attributes Sprit...

Page 51: ...1 Rows Y MSB 7 6 5 4 3 2 1 0 LSB 0 Color code for 0 0 Color code for 1 0 Color code for 2 0 Color code for 3 0 Base address 1 Color code for 4 0 Color code for 5 0 Color code for 6 0 Color code for 7 0 127 Color code for 508 0 Color code for 509 0 Color code for 510 0 Color code for 511 0 128 Color code for 0 1 Color code for 1 1 Color code for 2 1 Color code for 3 1 27135 Color code for 508 211 C...

Page 52: ...VDP can only display 4 solid colors in G5 mode however pixels are so small that combination of two pixels from the set of those 4 solid colors possible produces another visible color a mixture of the applied two This feature is only available in G5 mode and is applied to the sprites and to the screen border color G5 has 512 pixels in its X axis but sprites X coordinate is between 0 and 255 This me...

Page 53: ...ode 8 8 size Offset 7 6 5 4 3 2 1 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 1 2 3 4 5 6 7 Sprite pattern 8 8 MSB LSB 0 X X X 0 0 1 1 1 1 X X X 0 0 1 1 1 2 X X X 0 0 1 1 1 3 X X X 0 0 1 1 1 4 X X X 0 0 1 1 1 5 X X X 0 0 1 1 1 6 X X X 0 0 1 1 1 7 X X X 0 0 1 1 1 Sprite colors Sprite image how sprite is seen perceived by the user in G5 mode ...

Page 54: ... 108 2010 2015 Eugeny Brychkov Pattern name table Maximum of 4 pages may be allocated in the same manner if VDP has 128K bytes attached to it 02000h 04000h 192 lines 06000h 212 lines 06A00h 07000h 08000h 1FFFFh 07000h Sprite pattern table 07800h Sprite color table 07A00h Sprite attribute table 07A80h ...

Page 55: ...f 512 per screen Sprite mode Sprite mode 2 VRAM area per screen 64K bytes Controls Graphics VRAM pattern name table Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 1 0 1 0 0 MSX system default values BASIC SCREEN number Pattern layout bitmap Sprite patterns Sprite attributes Sprit...

Page 56: ... 1 X Y 191 0 191 1 191 2 191 511 191 LN 0 211 0 211 1 211 2 211 511 211 LN 1 Rows Y MSB 7 6 5 4 3 2 1 0 LSB 0 Color code for 0 0 Color code for 1 0 Base address 1 Color code for 2 0 Color code for 3 0 255 Color code for 510 0 Color code for 511 0 256 Color code for 0 1 Color code for 1 1 54270 Color code for 508 211 Color code for 509 211 54271 Color code for 510 211 Color code for 511 211 Pattern...

Page 57: ...ignored 3 8 3 Sprite settings Set the start address of the sprite attribute table in registers R 5 and R 11 set start address of the sprite pattern generator table in register R 6 For details about sprites please refer to section Sprite mode 2 MSB 7 6 5 4 3 2 1 0 LSB R 5 A14 A13 A12 A11 A10 1 1 1 Sprite attribute table low R 11 0 0 0 0 0 0 A16 A15 Sprite attribute table high R 6 0 0 A16 A15 A14 A1...

Page 58: ...NIPPON GAKKI CO Page 58 of 108 2010 2015 Eugeny Brychkov Maximum of 2 pages may be allocated in the same manner if VDP has 128K bytes attached to it 08000h 192 lines 0C000h 212 lines 0D400h 0F000h 10000h 1FFFFh 0F000h Sprite pattern table 0F800h Sprite color table 0FA00h Sprite attribute table 0FA80h ...

Page 59: ... per screen Sprite mode Sprite mode 2 VRAM area per screen 64K bytes Controls Graphics VRAM pattern name table Background color code Low order four bits of R 7 Sprites VRAM sprite attribute table VRAM sprite pattern table Mode flags Bit M5 R 0 M4 R 0 M3 R 0 M2 R 1 M1 R 1 Value 1 1 1 0 0 MSX system default values BASIC SCREEN number Pattern layout bitmap Sprite patterns Sprite attributes Sprite col...

Page 60: ...0 255 0 1 0 1 1 1 2 1 3 1 255 1 X Y 191 0 191 1 191 2 191 255 191 LN 0 211 0 211 1 211 2 211 255 211 LN 1 Rows Y MSB 7 6 5 4 3 2 1 0 LSB 0 Base address 1 Color code for 0 0 Color code for 1 0 Green Red Blue 255 256 Color code for 255 0 Color code for 0 1 27134 27135 Color code for 254 211 Color code for 255 211 Pattern layout table base address is stored in register R 2 and corresponds to the cell...

Page 61: ...BD1 BD0 Screen margin backdrop color Screen margin color 3 9 3 Sprite settings Set the start address of the sprite attribute table in registers R 5 and R 11 set start address of the sprite pattern generator table in register R 6 For details about sprites please refer to section Sprite mode 2 MSB 7 6 5 4 3 2 1 0 LSB R 5 A14 A13 A12 A11 A10 1 1 1 Sprite attribute table low R 11 0 0 0 0 0 0 A16 A15 S...

Page 62: ...NIPPON GAKKI CO Page 62 of 108 2010 2015 Eugeny Brychkov Maximum of 2 pages may be allocated in the same manner if VDP has 128K bytes attached to it 08000h 192 lines 0C000h 212 lines 0D400h 0F000h 10000h 1FFFFh 0F000h Sprite pattern table 0F800h Sprite color table 0FA00h Sprite attribute table 0FA80h ...

Page 63: ... 1 0 Invalid 0 0 0 1 Stop STOP 0 0 0 0 In G4 and G6 modes the lower one bit and in G5 mode the lower two bits are lost in registers related to X coordinate DX NX The process of execution of VDP commands consists of several steps Ensure that current mode is G4 G7 In other modes result is not guaranteed Check the bit 0 CE command execution flag in status register S 2 to be 0 If it s 1 then previous ...

Page 64: ...ee the table below for VRAM paging in various video modes GRAPHIC4 Address GRAPHIC5 0 0 255 0 0000h 0 0 511 0 Page 0 Page 0 0 255 255 255 0 255 511 255 0 256 255 256 08000h 0 256 511 256 Page 1 Page 1 0 511 255 511 0 511 511 511 0 512 255 512 10000h 0 512 511 512 Page 2 Page 2 0 767 255 767 0 767 511 767 0 768 255 768 18000h 0 768 511 768 Page 3 Page 3 0 1023 255 1023 1FFFFh 0 1023 511 1023 GRAPHI...

Page 65: ...ts of R 46 command register together with the command code Name Operation LO3 LO2 LO1 LO0 IMP DC SC 0 0 0 0 AND DC SC DC 0 0 0 1 OR DC SC DC 0 0 1 0 XOR DC SC DC 0 0 1 1 NOT DC SC 0 1 0 0 0 1 0 1 0 1 1 0 Invalid 0 1 1 1 TIMP If SC 0 then DC DC else DC SC 1 0 0 0 TAND If SC 0 then DC DC else DC SC DC 1 0 0 1 TOR If SC 0 then DC DC else DC SC DC 1 0 1 0 TXOR If SC 0 then DC DC else DC SC DC 1 0 1 1 ...

Page 66: ...0 0 0 DX8 DX Destination X 0 R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination Y R 40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 R 41 0 0 0 0 0 0 0 NX8 NX Number of dots in X axis R 42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 R 43 0 0 0 0 0 0 NY9 NY8 NY Number of dots in Y axis In G4 and G6 modes the lower one bit and in G5 mode the lower two bits are lost in registers related to X coordina...

Page 67: ...X 0 Right 1 Left X transfer direction 0 Down 1 Up Y transfer direction 0 VRAM 1 ExpRAM Destination select Step 4 Execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 1 1 1 HMMC cmd Step 5 Send data and wait for completion While command is being executed by VDP CE bit of status register S 2 will be set to 1 When command is complete it will be reset to 0 When VDP sets TR bit of status register S 2 to ...

Page 68: ... 108 2010 2015 Eugeny Brychkov Flowchart of HMMC execution from CPU point of view HMMC Start Set up VDP registers Execute command Read status register 2 Data transmit R 44 HMMC End End of command Transmit ready Yes CE 0 No CE 1 No TR 0 Yes TR 1 ...

Page 69: ...Step 1 Set necessary coordinates in command registers MSB 7 6 5 4 3 2 1 0 LSB R 34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 R 35 0 0 0 0 0 0 SY9 SY8 SY Source transfer point Y R 36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Source transfer point X R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination transfer point Y R 42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 R 43 0 0 0 0 0 ...

Page 70: ...5 0 MXD DIY DIX 0 Right 1 Left X transfer direction 0 Down 1 Up Y transfer direction 0 VRAM 1 ExpRAM Destination select Step 3 Execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 1 1 0 YMMM cmd Step 4 Wait for command execution completion While command is being executed by VDP CE bit of status register S 2 will be set to 1 When command is complete it will be reset to 0 ...

Page 71: ...B 7 6 5 4 3 2 1 0 LSB R 32 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 R 33 0 0 0 0 0 0 0 SX8 SX Source transfer point X R 34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 R 35 0 0 0 0 0 0 SY9 SY8 SY Source transfer point Y R 36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Destination transfer point X R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination transfer point Y R 40 NX7 NX6 NX5...

Page 72: ...t 1 Left X transfer direction 0 Down 1 Up Y transfer direction 0 VRAM 1 ExpRAM Source location select 0 VRAM 1 ExpRAM Destination location select Step 3 Execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 1 0 1 HMMM cmd Step 4 Wait for command execution completion While command is being executed by VDP CE bit of status register S 2 will be set to 1 When command is complete it will be reset to 0 ...

Page 73: ...DX6 DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Destination X R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination Y R 40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 R 41 0 0 0 0 0 0 0 NX8 NX Number of dots in X axis R 42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 R 43 0 0 0 0 0 0 NY9 NY8 NY Number of dots in Y axis In G4 and G6 modes the lower one bit and in G5 mode the lower two bits are ...

Page 74: ...dot G7 Step 3 Select destination memory and direction from base coordinate MSB 7 6 5 4 3 2 1 0 LSB R 45 0 MXD DIY DIX 0 Right 1 Left X transfer direction 0 Down 1 Up Y transfer direction 0 VRAM 1 ExpRAM Destination select Step 4 Execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 1 0 0 HMMV cmd Step 5 Wait for command execution completion While command is being executed by VDP CE bit of status regi...

Page 75: ... DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Destination X 0 511 R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination Y 0 1023 R 40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 R 41 0 0 0 0 0 0 0 NX8 NX Number of dots in X axis R 42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 R 43 0 0 0 0 0 0 NY9 NY8 NY Number of dots in Y axis Step 2 Set color register value The first byte transferred from CPU after...

Page 76: ...the LMMC command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 0 1 1 LO3 LO2 LO1 LO0 LMMC cmd Logical operation Step 5 Send data and wait for completion While command is being executed by VDP CE bit of status register S 2 will be set to 1 When command is complete it will be reset to 0 When VDP sets TR bit of status register S 2 to 1 application can send next data to the VDP color register R 44 CLR If TR bit is 0...

Page 77: ... 108 2010 2015 Eugeny Brychkov Flowchart of LMMC execution from CPU point of view LMMC Start Set up VDP registers Execute command Read status register 2 Data transmit R 44 LMMC End End of command Transmit ready Yes CE 0 No CE 1 No TR 0 Yes TR 1 ...

Page 78: ... registers MSB 7 6 5 4 3 2 1 0 LSB R 32 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 R 33 0 0 0 0 0 0 0 SX8 SX Source X 0 511 R 34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 R 35 0 0 0 0 0 0 SY9 SY8 SY Source Y 0 1023 R 40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 R 41 0 0 0 0 0 0 0 NX8 NX Number of dots in X axis R 42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 R 43 0 0 0 0 0 0 NY9 NY8 NY Number of dots in Y axis Step 2 Select source memory ...

Page 79: ... command Step 4 Execute the LMCM command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 0 1 0 LMCM cmd Step 5 Read dot color code and check fir command end Use status register S 7 to get the color code of the dot Format of color data depends on the graphics mode MSB 7 6 5 4 3 2 1 0 LSB S 7 C3 C2 C1 C0 G4 G6 C1 C0 G5 C7 C6 C5 C4 C3 C2 C1 C0 G7 Check CE bit of status register S 2 for command completion CE set to 0 ...

Page 80: ...rychkov Flowchart of LMCM execution from CPU point of view TR must be cleared before command execution LMCM Start Set up VDP registers Execute command Read status register 2 Read status register S 7 LMMC End Transmit ready Command end No TR 0 Yes TR 1 No CE 1 Yes CE 0 ...

Page 81: ...n command registers MSB 7 6 5 4 3 2 1 0 LSB R 32 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 R 33 0 0 0 0 0 0 0 SX8 SX Source transfer point X R 34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 R 35 0 0 0 0 0 0 SY9 SY8 SY Source transfer point Y R 36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Destination transfer point X R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination transfer po...

Page 82: ...0 VRAM 1 ExpRAM Source location select 0 VRAM 1 ExpRAM Destination location select Step 3 Define logical operation and execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 0 0 1 LO3 LO2 LO1 LO0 LMMM cmd Logical operation Step 4 Check for command completion CPU should check CE bit of status register S 2 to identify if VDP has completed execution of the command When command is being executed CE bit is...

Page 83: ...DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Destination X dots R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Destination Y dots R 40 NX7 NX6 NX5 NX4 NX3 NX2 NX1 NX0 R 41 0 0 0 0 0 0 0 NX8 NX Number of dots in X axis R 42 NY7 NY6 NY5 NY4 NY3 NY2 NY1 NY0 R 43 0 0 0 0 0 0 NY9 NY8 NY Number of dots in Y axis Step 2 Set color register value The color code to use when painting a...

Page 84: ... transfer direction 0 Down 1 Up Y transfer direction 0 VRAM 1 ExpRAM Destination select Step 4 Execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 1 0 0 0 LMMV cmd Step 5 Check for command completion CPU should check CE bit of status register S 2 to identify if VDP has completed execution of the command When command is being executed CE bit is set to 1 when command is complete CE bit will be reset to...

Page 85: ...10 bits MJ9 MJ0 with value in the range 0 1023 and short side is defined in registers R 42 and R 43 by 9 bits MI8 MI0 with value in the range 0 511 The units used are dots Video or expansion RAM DIY Min DX DY Maj DIX LINE execution order Step 1 Set necessary coordinates in command registers MSB 7 6 5 4 3 2 1 0 LSB R 36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Starting point X R 38...

Page 86: ...short side NX defines triangle s side by Y axis if this bit is 1 then long side NY defines triangle s side by Y axis and short side NX defines triangle s side by X axis MSB 7 6 5 4 3 2 1 0 LSB R 45 0 MXD DIY DIX MAJ 0 Long X 1 Long Y Long short axis definition 0 Right 1 Left X transfer direction 0 Down 1 Up Y transfer direction 0 VRAM 1 ExpRAM Destination location select Step 4 Define logical oper...

Page 87: ...arting point X R 34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 R 35 0 0 0 0 0 0 SY9 SY8 SY Starting point Y Step 2 Set color register value Color to search for should be coded in color register R 44 CLR Format of color data depends on the graphics mode MSB 7 6 5 4 3 2 1 0 LSB R 44 C3 C2 C1 C0 G4 G6 C1 C0 G5 C7 C6 C5 C4 C3 C2 C1 C0 G7 Step 3 Select destination memory direction from base coordinate and orienta...

Page 88: ... SRCH cmd Step 5 Check for command termination or completion and X coordinate Flag BD of the status register S 2 is set if coded color in register R 44 was found otherwise this bit is reset Current value of the X coordinate can be read from the status registers S 8 and S 9 MSB 7 6 5 4 3 2 1 0 LSB S 2 BD CE Set to 0 at the end or termination of the command Set to 1 if coded color is found MSB 7 6 5...

Page 89: ... 2010 2015 Eugeny Brychkov Flowchart of SRCH execution from CPU point of view SRCH Start Set up VDP registers Execute command Read status register 2 Read status registers S 8 and S 9 SRCH End Command end Color found No CE 1 Yes CE 0 No BD 0 Yes CE 0 ...

Page 90: ...d registers MSB 7 6 5 4 3 2 1 0 LSB R 36 DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 R 37 0 0 0 0 0 0 0 DX8 DX Target point X R 38 DY7 DY6 DY5 DY4 DY3 DY2 DY1 DY0 R 39 0 0 0 0 0 0 DY9 DY8 DY Target point Y Step 2 Set color register value Color of the dot should be coded in color register R 44 CLR Format of color data depends on the graphics mode It is possible to do logical operation on the existing and new c...

Page 91: ...lect Step 4 Define logical operation and execute the command MSB 7 6 5 4 3 2 1 0 LSB R 46 0 1 1 0 LO3 LO2 LO1 LO0 PSET cmd Logical operation Step 5 Check for command completion CPU should check CE bit of status register S 2 to identify if VDP has completed execution of the command When command is being executed CE bit is set to 1 when command is complete CE bit will be reset to 0 ...

Page 92: ...execution order Step 1 Set necessary coordinates in command registers MSB 7 6 5 4 3 2 1 0 LSB R 32 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 R 33 0 0 0 0 0 0 0 SX8 SX Source point X R 34 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 R 35 0 0 0 0 0 0 SY9 SY8 SY Source point Y Step 2 Select destination memory MSB 7 6 5 4 3 2 1 0 LSB R 45 0 MXS ARG 0 VRAM 1 ExpRAM Destination location select Step 3 Execute the command MSB 7...

Page 93: ...rmat of the data in various graphics mode differs MSB 7 6 5 4 3 2 1 0 LSB S 7 C3 C2 C1 C0 G4 G6 C1 C0 G5 C7 C6 C5 C4 C3 C2 C1 C0 G7 4 5 Speeding up the processing of VDP commands Programmer can use two methods to speed up VDP hardware acceleration commands Use of both methods is related to decreasing VDP access to the VRAM and freeing available VRAM time slots for command execution Disabling sprit...

Page 94: ...egisters from previous commands it is important to disable interrupts so that interrupt handler routing would not accidentally change values in VDP registers and thus break the whole command sequence CMR H is a higher nibble of the command register R 46 CMR L is a lower nibble of the command register r 46 ARG is an argument register R 45 The resulting values of SY DY and NY are in dots and can be ...

Page 95: ...endently switched on or off The following diagram conceptually shows how sprites are displayed Note that visible screen area may have 192 or 212 pixels depending on the setting of LN bit of register R 9 and visible screen area can be vertically scrolled using vertical offset register R 23 0 255 255 255 X Y Sprite Sprite Visible screen area 0 191 or 0 211 Invisible screen area 255 191 or 255 211 Sp...

Page 96: ...of displayed sprites on this line the sprites with higher priority will be displayed and the overlapping portions of lower priority sprites will not be displayed Lower sprite numbers are assigned higher priority with 0 is of highest priority and 31 is of lowest priority 0 3 4 1 2 5 When two sprites collide their pattern color 1 portions have overlapped status register s S 0 bit 5 C is set to 1 If ...

Page 97: ...ttribute table SM1 The sprite attribute table is an area in the VRAM that defines display coordinates for all the possible 32 sprites their colors pattern numbers used for display and some other flags Each sprite has four bytes of attribute data making up 128 bytes 80h of the memory MSB 7 6 5 4 3 2 1 0 LSB B 0 Y coordinate 0 255 1 X coordinate 0 255 2 Pattern number 0 255 3 EC Color code Attribute...

Page 98: ...ite bitmap image The dots which are set to 0 in the sprite bitmap image will appear transparent EC Early clock is used to offset sprite by 32 dots to the left This feature is useful when programmer needs to put sprite to the left off the screen 5 1 3 Sprite pattern generator table SM1 Sprite pattern generator table is an area in the VRAM specifying the sprite patterns appearance Base address of th...

Page 99: ...6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 Pattern 0 8 9 10 11 12 13 14 15 Pattern 1 16 16 16 sprite size mode pattern layout 17 18 19 20 21 0 2 22 23 Pattern 2 24 1 3 25 26 27 28 29 30 31 Pattern 3 Remember that in 16 16 sprite size mode two least significant bits of pattern number are not used and setting sprite pattern number 3 will display the same sprite image as setting sprite pattern num...

Page 100: ...iority and 31 is of lowest priority 0 3 4 5 7 1 2 6 8 When two sprites collide their solid 1 portions have overlapped status register s S 0 bit 5 C is set to 1 and the coordinates of the collision can be read from status registers S 3 S 5 If there re more than 8 sprites on the single horizontal line bit 6 of the status register S 0 5S is set to 1 and the lower order 5 bits of this status register ...

Page 101: ...r table which controls the appearance of the dots within the sprite being on 1 or off 0 sprite color table which control colors of the sprite lines and other attributes and sprite attribute table which controls positioning and used pattern number 5 2 2 Sprite attribute table SM2 The sprite attribute table is an area in the VRAM that defines display coordinates for all the possible 32 sprites patte...

Page 102: ... 16 16 mode two lower order bits of the pattern number are not used and they can hold any value Color code is not used in sprite mode 2 and the respective area in the table is reserved MSB 7 6 5 4 3 2 1 0 LSB R 5 A14 A13 A12 A11 A10 1 X X Sprite attribute table low SM2 R 11 0 0 0 0 0 0 A16 A15 Sprite attribute table high SM2 5 2 3 Sprite pattern generator table SM2 Sprite pattern generator table i...

Page 103: ...less TP bit of register R 8 is set Each entry also defines sprite priority collision detection and early clock sprite display options The base address of the sprite color table is calculated using base address of the sprite attribute table sprite color table is located strictly above the sprite attribute table having base address of sprite attribute table minus 512 200h Every sprite is assigned 16...

Page 104: ...s SM2 In sprite mode 2 SM2 if the CC bit of the sprite color table entry is set to 1 the sprite priority mechanism is cancelled for the specified line Collision mechanism does not work mixing color codes of the lines of affected sprites using OR logical operation This logical color mixing will work for sprite N if its affected line has CC bit set and this line will collide with the line of another...

Page 105: ...set to 0 MSB LSB Sprite N 1 0 1 0 0 Color code 4 4 CC all set to 1 MSB LSB Sprite N 2 0 0 1 0 Color code 2 2 CC all set to 1 Resulting images in SM1 and SM2 modes all sprites are placed at the same X Y 12 4 4 8 6 8 1 4 1 0 2 2 Sprite mode 2 CC flag is used no collision detection Sprite mode 1 collision detection turned on ...

Page 106: ... This bit will be reset when S 0 is read When collision occurs and neither mouse flag MO nor the light pen flag LP of the register R 8 are set status registers S 3 to S 6 will contain coordinates of the collision When status register S 5 is read all the contents of registers S 3 to S 6 are reset This means that program should read status registers S 3 S 4 and S 6 before reading status register S 5...

Page 107: ...1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 The state of bit 5 TP of register R 8 affects how sprites are displayed and affects color code 0 TP bit value Behavior TP 0 Color code 0 will be treated as transparent and invisible All the do...

Page 108: ...nd 2053 ms may be specified for each page See section 3 2 6 for information about available time periods Specify the odd page address in the pattern layout table register R 2 Specify ON even page and OFF odd page display intervals in register R 13 6 2 Displaying two graphics screens at 60Hz Bit 2 EO of register R 9 can be used for displaying two graphics screens alternately at 60Hz Set the odd pag...

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