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RSio64-D
2-6. WORD CLOCK inspection
Contents:
Word clock source register is cleared. (It carries
out before an inspection.)
Inside WORD CLOCK is inspected.
SLOT(MY1) WORD CLOCK is inspected.
SLOT(MY2) WORD CLOCK is inspected.
SLOT(MY3) WORD CLOCK is inspected.
SLOT(MY4) WORD CLOCK is inspected.
Exterior WORD CLOCK is inspected.
DANTE WORD CLOCK is inspected.
(Example of screen)
OUTPUT result
• Normal condition
The result is displayed in Output window as below.
* “MIN: xxxxh, MAX: xxxxh” represents a hexadecimal
counted value.
Item
Character string to be displayed
Word Clock CLR
OK: FPGA WCK CLR
Word Clock MY1
OK: FPGA WCK MY1
MIN: xxxxh, MAX: xxxxh
Word Clock MY2
OK: FPGA WCK MY2
MIN: xxxxh, MAX: xxxxh
Word Clock MY3
OK: FPGA WCK MY3
MIN: xxxxh, MAX: xxxxh
Word Clock MY4
OK: FPGA WCK MY4
MIN: xxxxh, MAX: xxxxh
Word Clock EXT
OK: FPGA WCK EXT
MIN: xxxxh, MAX: xxxxh
Word Clock DNT
OK: FPGA WCK DNT
MIN: xxxxh, MAX: xxxxh
• In case of failure
The result is displayed in Output window as below.
* “MIN: xxxxh, MAX: xxxxh” represents a hexadecimal
counted value.
Item
Character string to be displayed
Word Clock CLR
NG: FPGA WCK CLR
Word Clock MY1
NG: FPGA WCK MY1
MIN: xxxxh, MAX: xxxxh
Word Clock MY2
NG: FPGA WCK MY2
MIN: xxxxh, MAX: xxxxh
Word Clock MY3
NG: FPGA WCK MY3
MIN: xxxxh, MAX: xxxxh
Word Clock MY4
NG: FPGA WCK MY4
MIN: xxxxh, MAX: xxxxh
Word Clock EXT
NG: FPGA WCK EXT
MIN: xxxxh, MAX: xxxxh
Word Clock DNT
NG: FPGA WCK DNT
MIN: xxxxh, MAX: xxxxh
2-7. DM9000 Inspection
Contents:
Link with DM9000 and built-in switch on Dante
board is inspected.
(Example of screen)
OUTPUT result
• Normal condition
The result is displayed in Output window as below.
* “xxx.xxx.xxx.xxx” represents an IP address.
Item
Character string to be displayed
Net State
OK: IP=xxx.xxx.xxx.xxx
• In case of failure
The result is displayed in Output window as below.
Item
Character string to be displayed
Net State
NG: Cannot get local addr
NG: Cannot convert local addr