Yamaha RSio64-D, Service Manual, Page: 28 / 136

28
RSio64-D
PIN
NO. OUTER
NO.
NAME I/O FUNCTION NAME(DM-IC301) I/O
291 M5 GND - Ground. GND -
292 M6 IO_L55P_M3A13_3 I/O Memory controller address A[0:14] in bank 3. NC -
293 M7 VCCO 3 - Power-supply pins for the output drivers (per bank). VCCO -
294 M8 IO_L53N_M3A12_3 O Memory controller address A[0:14] in bank 3. NC -
295 M9 IO_L53P_M3CKE_3 O Memory controller clock enable in bank 3. NC -
296 M10 IO_L51P_M3A10_3 O Memory controller address A[0:14] in bank 3. NC -
297 M11 VCCINT - Power-supply pins for the internal core logic. VCCINT -
298 M12 GND - Ground. GND -
299 M13 VCCINT - Power-supply pins for the internal core logic. VCCINT -
300 M14 GND - Ground. GND -
301 M15 VCCINT - Power-supply pins for the internal core logic. VCCINT -
302 M16 GND - Ground. GND -
303 M17 VCCAUX - Power-supply pins for auxiliary circuits. VCCAUX -
304 M18 IO_L36P_A9_M1BA0_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller bank address BA[0:2] in bank 1. NC -
305 M19 IO_L34P_A13_M1WE_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller write enable in bank 1. NC -
306 M20 VCCO 1 - Power-supply pins for the output drivers (per bank). VCCO -
307 M21 IO_L40N_GCLK10_M1A6_1 I • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
NC -
308 M22 GND - Ground. GND -
309 M23 IO_L31P_A19_M1CKE_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller clock enable in bank 1. NC -
310 M24 IO_L23P_M5UDQS_5 I/O Memory controller upper data strobe in bank 5. NC -
311 M25 VCCO 5 - Power-supply pins for the output drivers (per bank). VCCO -
312 M26 IO_L23N_M5UDQSN_5 I/O Memory controller upper data strobe N in bank 5. MD[1] I/O
313 N1 IO_L59N_M4DQ15_4 I/O Memory controller data D[0:15] in bank 4 WC2DNT O
314 N2 IO_L59P_M4DQ14_4 I/O Memory controller data D[0:15] in bank 4. NC -
315 N3 IO_L52N_M3A9_3 O Memory controller address A[0:14] in bank 3. NC -
316 N4 IO_L52P_M3A8_3 O Memory controller address A[0:14] in bank 3. NC -
317 N5 IO_L50N_M3BA2_3 O Memory controller bank address BA[0:2] in bank 3. NC -
318 N6 IO_L47N_M3A1_3 O Memory controller address A[0:14] in bank 3. NC -
319 N7 IO_L47P_M3A0_3 O Memory controller address A[0:14] in bank 3. NC -
320 N8 IO_L43P_GCLK23_M3RASN_3 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller active-Low row address strobe in bank 3.
NC -
321 N9 IO_L51N_M3A4_3 O Memory controller address A[0:14] in bank 3. NC -
322 N10 VCCAUX - Power-supply pins for auxiliary circuits. VCCAUX -
323 N11 GND - Ground. GND -
324 N12 VCCINT - Power-supply pins for the internal core logic. VCCINT -
325 N13 GND - Ground. GND -
326 N14 VCCINT - Power-supply pins for the internal core logic. VCCINT -
327 N15 GND - Ground. GND -
328 N16 VCCINT - Power-supply pins for the internal core logic. VCCINT -
329 N17 IO_L38P_A5_M1CLK_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller clock in bank 1. NC -
330 N18 IO_L38N_A4_M1CLKN_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller active-Low clock in bank 1. NC -
331 N19 IO_L36N_A8_M1BA1_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller bank address BA[0:2] in bank 1. NC -
332 N20 IO_L40P_GCLK11_M1A5_1 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
NC -
333 N21 IO_L30N_A20_M1A11_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. NC -
334 N22 IO_L37P_A7_M1A0_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. NC -
335 N23 IO_L37N_A6_M1A1_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. NC -
336 N24 IO_L31N_A18_M1A12_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. NC -
337 N25 IO_L25P_M5DQ14_5 I/O Memory controller data D[0:15] in bank 5 MD[2] I/O
338 N26 IO_L25N_M5DQ15_5 I/O Memory controller data D[0:15] in bank 5 MD[3] I/O
339 P1 IO_L48N_M3BA1_3 O Memory controller bank address BA[0:2] in bank 3. NC -
340 P2 GND - Ground. GND -
341 P3 IO_L48P_M3BA0_3 O Memory controller bank address BA[0:2] in bank 3. NC -
342 P4 VCCO 3 - Power-supply pins for the output drivers (per bank). VCCO
343 P5 IO_L50P_M3WE_3 O Memory controller write enable in bank 3. NC -
344 P6 IO_L45N_M3ODT_3 O Memory controller on-die termination control for external memory in bank 3. NC -
345 P7 IO_L45P_M3A3_3 O Memory controller address A[0:14] in bank 3. NC -
346 P8 IO_L43N_GCLK22_IRDY2_M3CASN_3 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Used with LogiCORE IP for PCI designs.
• Memory controller active-Low column address strobe in bank 3.
NC -
347 P9 VCCO 3 - Power-supply pins for the output drivers (per bank). VCCO -
348 P10 IO_L49P_M3A7_3 O Memory controller address A[0:14] in bank 3. NC -
349 P11 VCCINT - Power-supply pins for the internal core logic. VCCINT -
350 P12 GND - Ground. GND -
351 P13 VCCINT - Power-supply pins for the internal core logic. VCCINT -
352 P14 GND - Ground. GND -
353 P15 VCCINT - Power-supply pins for the internal core logic. VCCINT -