Yamaha RSio64-D, Service Manual, Page: 29 / 136

29
RSio64-D
PIN
NO. OUTER
NO.
NAME I/O FUNCTION NAME(DM-IC301) I/O
354 P16 GND - Ground. GND -
355 P17 IO_L56P_1 I/O User I/O pin NC -
356 P18 IO_L56N_1 I/O User I/O pin NC -
357 P19 GND - Ground. GND -
358 P20 IO_L30P_A21_M1RESET_1 I/O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller reset in bank 4. NC -
359 P21 IO_L41P_GCLK9_IRDY1_M1RASN_1 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Used with LogiCORE IP for PCI designs.
• Memory controller active-Low column address strobe in bank 3.
NC -
360 P22 IO_L41N_GCLK8_M1CASN_1 O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller active-Low column address strobe in bank #.
NC -
361 P23 VCCO 1 - Power-supply pins for the output drivers (per bank). VCCO -
362 P24 IO_L33P_A15_M1A10_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. NC -
363 P25 GND - Ground. GND -
364 P26 IO_L33N_A14_M1A4_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. MD[4] I/O
365 R1 IO_L44N_GCLK20_M3A6_3 I • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
SCLKFDNT I
366 R2 IO_L44P_GCLK21_M3A5_3 I • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller address A[0:14] in bank 1.
NC -
367 R3 IO_L46N_M3CLKN_3 O Memory controller active-Low clock in bank 3. NC -
368 R4 IO_L46P_M3CLK_3 O Memory controller clock in bank 3. NC -
369 R5 IO_L30P_3 I/O User I/O pin NC -
370 R6 IO_L31N_VREF_3 - These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. NC -
371 R7 IO_L31P_3 I/O User I/O pin NC -
372 R8 GND - Ground. GND -
373 R9 IO_L49N_M3A2_3 O Memory controller address A[0:14] in bank 3. NC -
374 R10 IO_L27P_3 I/O User I/O pin NC -
375 R11 GND - Ground. GND -
376 R12 VCCINT - Power-supply pins for the internal core logic. VCCINT -
377 R13 GND - Ground. GND -
378 R14 VCCINT - Power-supply pins for the internal core logic. VCCINT -
379 R15 GND - Ground. GND -
380 R16 VCCINT - Power-supply pins for the internal core logic. VCCINT -
381 R17 IO_L58P_1 I/O User I/O pin NC -
382 R18 IO_L58N_1 I/O User I/O pin NC -
383 R19 IO_L57N_1 I/O User I/O pin NC -
384 R20 IO_L57P_1 I/O User I/O pin NC -
385 R21 IO_L55N_1 I/O User I/O pin NC -
386 R22 IO_L55P_1 I/O User I/O pin NC -
387 R23 IO_L39P_M1A3_1 O Memory controller address A[0:14] in bank 1. NC -
388 R24 IO_L39N_M1ODT_1 O Memory controller on-die termination control for external memory in bank 1. NC -
389 R25 IO_L35P_A11_M1A7_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. MD[5] I/O
390 R26 IO_L35N_A10_M1A2_1 O • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• Memory controller address A[0:14] in bank 1. MD[6] I/O
391 T1 IO_L41N_GCLK26_M3DQ5_3 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller data D[0:15] in bank 3.
MCLKFDNT I
392 T2 VCCO 3 - Power-supply pins for the output drivers (per bank). VCCO -
393 T3 IO_L41P_GCLK27_M3DQ4_3 I/O • These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for
clocks.
• Memory controller data D[0:15] in bank 3.
NC -
394 T4 IO_L30N_3 I/O User I/O pin NC -
395 T5 GND - Ground. GND -
396 T6 IO_L29N_3 I/O User I/O pin NC -
397 T7 VCCO 3 - Power-supply pins for the output drivers (per bank). VCCO -
398 T8 IO_L29P_3 I/O User I/O pin NC -
399 T9 IO_L27N_3 I/O User I/O pin NC -
400 T10 IO_L25P_3 I/O User I/O pin NC -
401 T11 VCCINT - Power-supply pins for the internal core logic. VCCINT -
402 T12 GND - Ground. GND -
403 T13 VCCINT - Power-supply pins for the internal core logic. VCCINT -
404 T14 GND - Ground. GND -
405 T15 VCCINT - Power-supply pins for the internal core logic. VCCINT -
406 T16 GND - Ground. GND -
407 T17 VCCINT - Power-supply pins for the internal core logic. VCCINT -
408 T18 IO_L60P_1 I/O User I/O pin NC -
409 T19 IO_L60N_1 I/O User I/O pin NC -
410 T20 IO_L64P_1 I/O User I/O pin NC -
411 T21 GND - Ground. GND -
412 T22 IO_L59P_1 I/O User I/O pin NC -
413 T23 IO_L53P_1 I/O User I/O pin NC -
414 T24 IO_L46P_FCS_B_M1DQ2_1 O • BPI flash chip select.
• Memory controller data D[0:15] in bank 1. NC -
415 T25 VCCO 1 - Power-supply pins for the output drivers (per bank). VCCO -