Yamaha neoHD YMC-700, Service Manual

Page: 77 / 101

★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
77
DIGITAL 3/8
YMC-700/YMC-500
IC331
IC334 IC334
IC334 IC334
IC334
IC333
IC332
POINT C XL331 (Pin 1 of IC334)
C
0
0.5
0.2
0.4
0
0.4
0.3
0.3
0
3.3
0
3.3
0
0
0
0
3.1
0
0
3.3
3.3
1.3
3.3
3.3
0
0.4
0.3
3.1
1.4
0
0.2
0
0.2
0.2
1.9
0.2
0.2
0.3
1.8
3.3
0
0
0
1.3
0
1.8
1.6 1.6
1.8
3.3
0
3.3
0
1.6
1.3
0
0
0.2 0.2 0.2 0.2 0.2 0.2
3.3
3.3 0.2
0
1.3
0.2 0.2 3.1 0.2
0
0.3 0.3
0
1.6
0 0 0
0.5 0.6 0.7
3.3
0 0
3.3
3.0
0 0 0
0.7
0
1.9 1.4 1.9
0 0
0.8 0.8 0.7
3.3
1.3
3.3
3.3
0.2
0
0
0
0
0
3.3
0
0 1.7
3.3
0.4 0.2 0.3 3.2 0 0 0 0 0 0.4 0.3 0.3 0.4
1.3 3.3
3.0 0 0 0 0 0.4 1.3
3.3 1.3
0 0 0 0 0 2.5 0 0
3.3
3.3 0 3.1 0 0 0 3.3
3.3
0 0 0
1.3
0
0 0 0
1.3
0
0
1.3
1.3 3.3
1.3
1.3
1.3
0
2.5
2.5
2.5
0
1.3
3.3
3.3
0
3.3 0.2 0.2
0
0.2 0.2 3.3 0.2 0.2
0
3.3 3.3
0
3.0 1.9 1.4 1.9
0 0
0
0.8 0.8 0.7 0.7 3.3
0 0.2 0 0.2 0.2 3.3 3.1 0.2 0 0.2 0.3 3.3 0.3 0 0
1.6 3.3
0 0 0 0.5 0.6 0.7 0.7 0
0
1.3
0
0
0
0
0
0
0
0
0
0
3.3
0
0
0
0
1.8
1.8
1.8
0
0
1.7
0
3.3
0
3.3
3.3
3.3
1.3
0
3.3
0
0
0
0
0
0
0
3.3
0
3.3
3.3
0.7
0
0
0
0
3.3
0
VDD
A3
A2
A1
A0
A10/AP
A12
A13
CS
RAS
CAS
WE
LDQM
VDD
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDDQ
VDDQ
VSSQ
DQ0
VDD
VSS
A4
A5
A6
A7
A8
A9
A11
NC
CKE
CLK
UDQM
NC
VSS
VDDQ
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSSQ
VSSQ
VDDQ
DQ15
VSS
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
IC332 : M12L64164A-5TG
1M x 16-bit x 4 banks synchronous DRAM
CLK
CS
RAS
CAS
WE
C
ommand Decoder
C
ontr
ol Logic
Latch Cir
cuit
Input & Output
Buf
fer
R
o
w Decoder
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
L(U)DQM
DQ
CKE
Address
Clock
Generator
Row
Address
Buffer
Column
Address
Buffer
&
&
Refresh
Counter
Refresh
Counter
Mode
Register
Bank B
Bank C
Bank D
V
DD
CE
Pin No.
1
2, 5
3
4
6
Symbol
VOUT
GND
CE
NC
VDD
Description
Output Pin of Voltage Regulator
Ground Pin
Chip Enable Pin
No Connection
Input Pin
Vref
6 1
3 2,5
Current Limit
V
OUT
GND
IC333 : R1172S121D-E2-F
Voltage regulator
IC334 : 74LVC3GU04DP
Triple inverter
1 1A
3Y
2
3
GND 4
2A
8 Vcc
7
6
1Y
5
3A
2Y
No replacement part available.
FPGA
SDRAM
YMC-500
to DIGITAL 5/8
to DIGITAL 4/8
to DIGITAL 6/8
to DIGITAL 1/8
to DIGITAL 1/8
to DIGITAL 3/8
to DIGITAL 5/8
to DIGITAL 5/8
to DIGITAL 5/8
to DIGITAL 5/8
to DIGITAL 5/8
to DIGITAL 4/8
to DIGITAL 4/8
to DIGITAL 4/8
to DIGITAL 2/8
to DIGITAL 2/8
to DIGITAL 2/8
to DIGITAL 5/8
YMC-700
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL 13942296513 QQ 376315150 892498299 TEL 13942296513 QQ 376315150 892498299
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