Yamaha neoHD YMC-700, Service Manual

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50
YMC-700/YMC-500
YMC-70
0/YMC-50
0
Blackfin PF Ports
SPORT0
Synchronous memory control
Memory Interface
PPI
UART
TMR Ports (Used as General Output Ports (TMR0 and
PPI sync ports (PPI) )
Pin
No.
Port
Name
Function Name I/O Detail of Function
51 PF0 ADC_N_CS O AD converter chip select
50 PF1 3.3S_N_ON O +3.3S power supply control
49 PF2 EEPROM_N_CS O EEPROM chip select
48 PF3 BF_PPI_FIELD O GUI field signal
47 PF4 BANK_SEL1 O
Flash memory bank select
signal
46 PF5 PWS_N_ON I Front panel power switch
38 PF6 PWR_N_PDET I Sub trans power detection
37 PF7 REM I Front panel IR receiver
36 PF8 NPGA_INT I NPGA interrupt request
35 PF9 BANK_SEL0 O
Flash memory bank select
signal
34 PF10 PWR_RY_ON O Main trans relay control
33 PF11 EXTP1_N_OE O
Extended por ts 1 output
Enable
32 PF12 – – –
Pin
No.
Port
Name
Function Name I/O Detail of Function
79 TMR0 USB_N_RST O Front panel LED control
78 TMR1 BF_PPI_HS O PPI H-sync
77 TMR2 BF_PPI_VS O PPI V-sync
Pin
No.
Port
Name
Function Name I/O Detail of Function
21 PPI_CLK BF_PPI_CLK I PPI input clock
22 PP10
BF_PPI[0-7] O PPI output data
23 PP11
24 PP12
25 VDDINT
26 PP13
27 PF15
28 PF14
29 PF13
Pin
No.
Port
Name
Function Name I/O Detail of Function
81 TX BF_UART_TX O UART Tx
82 RX BF_UART_RX I/O UART Rx
Pin
No.
Port
Name
Function Name I/O Detail of Function
76 RSCLK0 –
I (no use)
75 RFS0 –
74 DR0PRI –
73 DR0SEC –
72 TSCLK0 DIR_SCK I SPORT0 Tx SCLK input
69 TFS0 DIR_WCK I SPORT0 Tx FS input
68 DT0PRI
B F _ S P O R T _
SDO
O SPORT0 Tx data output
67 DT0SEC – O (no use)
Pin
No.
Port
Name
Function Name I/O Detail of Function
65 RSCLK1 –
I (no use)
64 RFS1 –
63 DR1PRI –
62 DR1SEC –
61 TSCLK1 –
60 TFS1 –
59 DT1PRI –
O (no use)
58 DT1SEC –
Pin
No.
Port
Name
Function Name I/O Detail of Function
121 ADDR19
– O
Address bus for async/Sync
access
122 ADDR18
123 ADDR17
124 ADDR16
125 ADDR15
126 ADDR14
127 ADDR13
135 ADDR12
– O
Address bus for async/Sync
access
136 ADDR11
137 ADDR10
138 ADDR9
139 ADDR8
140 ADDR7
141 ADDR6
142 ADDR5
146 ADDR4
– O
Address bus for async/Sync
access
147 ADDR3
148 ADDR2
149 ADDR1
98 DATA15
– I/O Data bus for async access
99 DATA14
100 DATA13
101 DATA12
102 DATA11
103 DATA10
104 DATA9
105 DATA8
108 DATA7
– I/O Data bus for async access 109 DATA6
110 DATA5
112 DATA4
– I/O Data bus for async access
113 DATA3
114 DATA2
115 DATA1
116 DATA0
150 ABE1
– O
Byte enables/Data masks
for async/Sync access 151 ABE0
163 BR – I
Bus request (This pin should
be pulled HIGH if not used.)
119 BG – O Bus grant
120 BGH – O Bus grant hang
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