Xycom XVME 200, Manual

Page: 9 / 57

XVME-200/290 Manual
December, 1987
The DIO Module uses two 68230 Parallel Interface/Timer devices to provide a total
of 32 parallel I/O lines (16 lines per chip) arranged as four I/O ports (two 8 line
ports per chip), as well as 2 programmable timers (1 timer per chip).
Several
different operating modes can be programmed for the parallel ports and timers, to
provide a high degree of versatility and flexibility.
Each 68230 chip has two (8 line) I/O ports labeled as Port Al and Port Bl for PI/T
#l, and Port A2 and Port B2 for PI/T #2. The third Port on each PI/T chip (Port
C/Alternate Function) is configured as a group of dedicated control lines for
interrupt handling, timer operation, and data port direction.
Each of the four I/O ports is independently buffered by its own 8-bit data
transceiver. The data transceivers are all bidirectional, with their direction being
independently controlled by PC0 and PC1 of the Port D/Alternate Function lines on
each PI/T.
The 8 data lines within each of the four PI/T I/O ports Al, A2, Bl,
and B2 must always be programmed for the same direction (i.e., because transceiver
data direction is programmed individually for each port and cannot be done on a
line-by-line basis).
In order to avoid signal direction contention between a PI/T
Port and its data transceiver, the direction of the ports and transceivers must be
programmed in the proper order (documented in Chapter 2).
The DIO Module design allows each of the PI/T ports Al, Bl, A2, or B2 to be
individually programmed in either Port Mode 0 or Port Mode 1 (refer to the 68230
Manual for a description of Port Modes).
In addition, any of the submodes within
Port Modes 0 and 1 may be utilized. There are 4 buffered handshake lines for each
PI/T chip which (depending on the operation mode selected and the position of
jumpers Jl and J3) can be used to provide interlocked handshake, pulsed handshake,
interrupt input (independent of data transfer), or general purpose single-line I/O.
Each PI/T chip also contains its own 24-bit timer capable of signaling event
occurrence by generating a periodic interrupt, an interrupt after timeout, or a
square wave output.
The timer interrupt capability is enabled by using three of the
Port C/Alternate Function pins programmed to carry the Timer Interrupt functions
(i.e., Timer Interrupt enable, Timer input, and Timer output).
The module address decode logic allows the user to select (via 6 jumpers) any one
of 64 of the 1K boundaries in the Short I/O Address Space to be used as the
module base address.
The PI/T Internal Registers are accessible at specific
addresses offset from the selected module base address. Any of the 7 VMEbus
interrupt levels may be selected (via 3 jumpers) to facilitate interrupt generation,
and handling from any one of 4 interrupt sources on the module (i.e., PI/T #l port
interrupts, PI/T #2 port interrupts, PI/T #l timer interrupts, and PI/T #2 timer
interrupts).
Each of the two PI/T chips is capable of producing 5 different IACK
vectors (one for the timer and four for the ports) for a total of ten different IACK
vectors per module.
On the XVME-200/290 the configuration of the
I/O signals interface to JKl or JK2 (XVME-200,
I/O signals connect to (XVME-290/l), and the
direction of H2, which must be distinct. PI/Ts differ only in whether their
XVME-290/2) or which P2 pins the
jumper number which controls the
.
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