XVME-2001290 Manual
December, 1987
Table 3-l. Register
Offsets From the Module Base
Address
68230 PI/T Register Offsets from Module Base Address
PI/T #l
DEC HEX
1
1
3 3
5 5
7
7
9
9
1 1
B
1 3
D
1 5
F
1 7
11
1 9
1 3
2 1
1 5
2 3
1 7
2 5
1 9
27
1B
2 9
1D
3 1
1F
3 3
2 1
3 5
2 3
37
25
39
27
4 1
29
43
2B
45
2 D
47
2 F
49
3 1
5 1
3 3
5 3
3 5
5 5
3 7
57
39
59
3B
6 1
3 D
6 3
3 F
PI/T #2
DEC HEX
PI/T Register Name
6 5
4 1
Port General Control Register
6 7
43
Port Service Request Register
69
45
Port A Data Direction Register
7 1
47
Port B Data Direction Register
7 3
49
Port C Data Direction Register
7 5
4B
Port Interrupt Vector
7 7
4 D
Port A Control Register
79
4 F
Port B Control Register
8 1
5 1
Port A Data Register
8 3
53
Port B Data Register
8 5
55
Port A Alternate Register
8 7
57
Port B Alternate Register
8 9
59
Port C Data Register
9 1
5B
Port Status Register
9 3
5D
Null
9 5
5 F
Null
97
6 1
Timer Control Register
9 9
6 3
Timer Interrupt Vector
1 0 1
65
Null
1 0 3
67
Counter Preload High
1 0 5
69
Counter Preload Middle
1 0 7
6B
Counter Preload Low
1 0 9
6 D
Null
1 1 1
6 F
Count Register High
1 1 3
7 1
Count Register Middle
1 1 5
73
Count Register Low
1 1 7
75
Timer Status Register
1 1 9
77
Null Registers Always
1 2 1
79
Read Zero. Writing
123 7B
To A Null Register
125 7D
Has No Effect On
1 2 7
7 F
The Module.
3-2
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