Xilinx Vivado MIPI CSI-2, Product Manual

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MIPI CSI-2 RX Subsystem v4.0 49
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
MIPI CSI-2 RX Controller Core Programming
The MIPI CSI-2 RX Controller programming sequence is as follows and Figure 3-9 shows a
graphical representation of the sequence:
1. After power on reset (
video_aresetn
), the core enable bit is, by default, set to 1 so
the core starts processing packets sent on the PPI. The Active Lanes parameter is set to
Maximum Lanes (configured in the Vivado IDE using the Serial Data Lanes parameter).
2. Disabling and re-enabling the core
°
Disable the core using the Core Configuration Register (set the Core Enable bit to 0
or the Soft reset bit to 1).
°
Wait until the core clears the Soft reset/Core enable in progress bit by reading the
Core Status Register .
°
Change the required core settings (for example, active lanes configuration, enabling
interrupts)
°
Re-enable the core (set the Core Enable bit to 1 or the Soft Reset bit to 0)
Active Lanes Configuration
The Protocol Configuration Register [1:0] can be used to dynamically configure the active
lanes used by the subsystem using the following guidelines:
1. Program the required lanes in the Protocol Configuration register (only allowed when
Enable Active Lanes is set in the Vivado IDE).
2. The subsystem internally updates the new lanes information after the current packet
complete indication is seen (for example, when the current active lanes indicate a Stop
state condition) and a subsequent RxByteClkHS signal is seen on the PPI.
3. A read from the Protocol Configuration register reflects the new value after the
subsystem has successfully updated the new lanes information internally.
4. Do not send the new updated lanes traffic until the read from Protocol Configuration
registers reflects the new value.
X-Ref Target - Figure 3-9
Figure 3-9: Core Programming Sequence
lite_aclk
Core Enable
Core Status[0]
Disable operation in progress
change settings
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