MIPI CSI-2 RX Subsystem v4.0
28
PG232 July 02, 2019
Chapter 2:
Product Specification
provide detailed information about the bits in
3
Frame synchronization
error for VC1
(ErrFrameSync)
0x0
R/W1C Asserted when an FE is not paired with a FS on
the same virtual channel
2
Frame level error for VC1
(ErrFrameData)
0x0
R/W1C
Asserted after an FE when the data payload
received between FS and FE contains errors.
The data payload errors are CRC errors.
1
Frame synchronization
error for VC0
(ErrFrameSync)
0x0
R/W1C Asserted when a FE is not paired with a FS on
the same virtual channel
0
Frame level error for VC0
(ErrFrameData)
0x0
R/W1C
Asserted after an FE when the data payload
received between FS and FE contains errors.
The data payload errors are CRC errors.
Notes:
1. W1C = Write 1 to clear.
2. In a line buffer full condition, reset the core using the external reset, video_aresetn.
3. Reported through the PPI.
4. An ErrSotSyncHS error also generates this error signal.
5. Short packet and line buffer FIFO full conditions take a few clock periods to reflect in the register clock domain
from the core clock domain due to Clock Domain Crossing (CDC) blocks.
6. All PPI signals captured in the ISR take a few clock periods to reflect in the register clock domain from the PPI clock
domain due to CDC blocks.
7. Frame level errors due to ErrSotSyncHS are mapped to the recent VC processed by the ECC block of the core.
8. Set conditions take priority over the reset conditions for the ISR bits.
9. Signal names in brackets are defined in the
MIPI Alliance Standard for Camera Serial Interface CSI-2
Table 2-13:
Incorrect Lane Configuration
Set Condition(s)
Set by the core when incorrect lane configuration is programmed.
Ex: Maximum available lanes =2 and “Active lanes” configured as 3
Reset Sequence Write 1 to clear this bit.
Priority
Set condition takes priority over reset sequence.
Impact
This is a core configuration error and the core cannot function as desired. This error
should be corrected before proceeding further.
Table 2-14:
Stream Line Buffer Full
Set Condition(s) Set by the core when the line buffer storing pixel data is full.
Reset Sequence Write 1 to clear this bit.
Priority
Set condition takes priority over reset sequence.
Impact
Core reports this condition on stream interface using an error indication on the
TUSER[1] port if a partial packet is being written to line buffer. Because PPI does not
allow back pressure, you need to ensure that this condition does not occur.
Table 2-12:
Interrupt Status Register (0x24)
(Cont’d)
Bits
Name
Reset
Value
Access
(1)
Description
