MIPI CSI-2 RX Subsystem v4.0
82
PG232 July 02, 2019
Appendix B:
Debugging
Answer Records for this subsystem can be located by using the Search Support box on the
main
. To maximize your search results, use proper keywords such
as:
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
For the MIPI CSI-2 Receiver Subsystem Master Answer Record see Xilinx Answer
Technical Support
Xilinx provides technical support at the
for this IP product when
used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support, navigate to the
Debug Tools
There are many tools available to address MIPI CSI-2 Receiver Subsystem design issues. It is
important to know which tools are useful for debugging various situations.
Vivado Design Suite Debug Feature
The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly
into your design. The debug feature also allows you to set trigger conditions to capture
application and integrated block port signals in hardware. Captured signals can then be
analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a
design running in Xilinx devices.
The Vivado logic analyzer is used with the logic debug IP cores, including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
See the
Vivado Design Suite User Guide: Programming and Debugging
(UG908)
.
