Xilinx Vivado MIPI CSI-2, Product Manual

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MIPI CSI-2 RX Subsystem v4.0 45
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
X-Ref Target - Figure 3-7
Figure 3-7: Clocking Structure
Table 3-2: Clocking
Clock Function Frequency Example
Rxbyteclkhs Byte clock for all
lane PPI operation.
1/8 of line rate Line rate = 1000 Mb/s
Rxbyteclkhs = 1000/8 = 125 MHz
Core
clock
Core clock for the
modules.
Lanes/4 of rxbyteclkhs Example 1
Line rate = 1000 Mb/s, Lanes = 4
Core clock = 125*4/4 = 125 MHz
Example 2
Lane rate = 1000 Mb/s, Lanes = 3
Core clock = 125*3/4 = 93.75 MHz
Pixel
clock
(1)(2)
Internal pixel clock For 8 bpp clock = core
clock/(32/8)
For 24 bpp clock = core
clock /(32/24)
/LQH5DWH
/DQHV
ESS
GLYLGHE\
ESS
GLYLGHE\
ESS
GLYLGHE\
ESS
GLYLGHE\
ESS
GLYLGHE\
ESS
GLYLGHE\
VLQJOH
GXDO
TXDG
rxbyteclkhs Core clock
Pixel Clock
Video Clock
Clock Dividers
;
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