62
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Appendix A:
Reference Information
R
vio_dn21
vio_dn5
IO_L07N_5/VREF_5_AD19
AD19
V4_IOB_L7_N
vio_dn22
vio_dn6
IO_L67N_5_AB15
AB15
V4_IOB_L15_N
vio_dn23
vio_dn7
IO_L67P_5_AA15
AA15
V4_IOB_L9_N_LC
vio_dn24
vio_dn8
IO_L06P_5/VRN_5_AB19
AB19
V4_IOB_L11P
vio_dn25
vio_dn9
IO_L73P_5_Y14
Y14
V4_IOB_L13_P
vio_dn_clk_ena
vio_dn_clk_ena
IO_L74N_5/GCLK5S_AC14
AC14
V4_IOB_L1_N
vio_reset
vio_reset
IO_L74P_5/GCLK4P_AB14
AB14
V4_IOB_L1_P
vio_sport_clk
vio_sport_clk
IO_L07P_5_AC19
AC19
V4_IOB_L3_N
vio_sport_sync
vio_sport_sync
IO_L69P_5_W15
W15
V4_IOB_L11_N
vio_sport_dn
vio_sport_dn
IO_L05_5/No_Pair_Y19
Y19
V4_IOB_L13_N
vio_sport_up
vio_sport_up
IO_L06N_5/VRP_5_AB18
AB18
V4_IOB_L3_P
vio_i2c_scl_up
vio_i2c_scl_up
IO_L09N_5/VREF_5_AA18
AA18
V4_IOB_L5_P
vio_i2c_sda_dn
vio_i2c_sda_dn
IO_L73N_5_AA14
AA14
V4_IOB_L24_N_LC
vio_i2c_sda_up
vio_i2c_sda_up
IO_L69N_5/VREF_5_W14
W14
V4_IOB_L15_P
vio_up_clk_lvds_N
vio_up_clk_lvds_N
IO_L75N_4/GCLK1S_AD13
AD13
V4_IOB_L22_N
vio_up_clk_lvds_P
vio_up_clk_lvds_P
IO_L75P_4/GCLK0P_AE13
AE13
V4_IOB_L22_P
Table A-4:
VIOBUS VIODC FPGA Connections
(Continued)
VIOBUS Single-
Ended Mode
Signal Name
VIOBUS
Differential Mode
Signal Name
VIODC
XCV2P4 FPGA
Pin Name
Pin
VIODC Schematic
Signal Name
www.BDTIC.com/XILINX