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Video Input/Output Daughter Card

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UG235 (v1.2.1) October 31, 2007

Bus Interface

Table 4-3:

Analog XGA60

Register Name

Register

Value

Description

Active Interface

0x12

0x81

Force selection of analog input

PLL Div MSB

0x01

0x53

PLL divider value. XGA60 has 1344 cycles per HSYNC
period. 1344 -1 = 0x53F

PLL Div LSB

0x02

0xF0

VCO/CPMP

0x03

0xB4

VCORNGE = 01, CURRENT = 101

Phase Adjust

0x04

0x80

Default phase = T/2

Clamp Placement

0x05

0x40

64 cycles after HSYNC

Clamp Duration

0x06

0x40

64 cycles in duration

HSOUT Pulse width

0x07

0x88

136 cycles in HSYNC

Table 4-4:

Analog SXGA60

Register Name

Register

Value

Description

Active Interface

0x12

0x81

Force selection of analog input

PLL Div MSB

0x01

0x69

PLL divider value. SXGA60 has 1688 cycles per HSYNC
period. 1688 -1 = 0x697

PLL Div LSB

0x02

0x70

VCO/CPMP

0x03

0xD0

VCORNGE = 10, CURRENT = 100

Phase Adjust

0x04

0x80

Default phase = T/2

Clamp Placement

0x05

0x64

100 cycles after HSYNC

Clamp Duration

0x06

0x64

100 cycles in duration

HSOUT Pulse width

0x07

0x70

112 cycles in HSYNC

Table 4-5:

Analog UXGA60

Register Name

Register

Value

Description

Active Interface

0x12

0x81

Force selection of analog input

PLL Div MSB

0x01

0x86

PLL divider value. UXGA60 has 2160 cycles per HSYNC
period. 2160 -1 = 0x86F

PLL Div LSB

0x02

0xF0

VCO/CPMP

0x03

0xD4

VCORNGE = 10, CURRENT = 101

Phase Adjust

0x04

0x80

Default phase = T/2

Clamp Placement

0x05

0x78

120 cycles after HSYNC

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Summary of Contents for VIODC

Page 1: ...R Video Input Output Daughter Card User Guide UG235 v1 2 1 October 31 2007 www BDTIC com XILINX ...

Page 2: ... to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXE...

Page 3: ... Input and Output 22 S Video Input 22 S Video Input Signal Conditioning 22 ADV7403 S Video Input 24 S Video Output 24 ADV7321 S Video Output 24 S Video Output Signal Conditioning 24 Composite Video Input and Output 24 Composite Video Input 25 Composite Video Input Conditioning Circuit 25 ADV7403 Composite Video Input 25 Composite Video Output 25 ADV7321A Composite Video Output 25 Composite Video C...

Page 4: ...ization Table in Hex 38 DVI 40 References to VGA DVI Standards 40 Chapter 5 DVI VGA Output Interface Overview 41 TPF410 I2C Configuration 42 Chapter 6 SDI Interface Introduction 43 Reference Clocks 43 SDI Receiver 44 PicoBlaze Controller for the ADV7321B Video Encoder 45 SDI Transmitter 48 References 49 Chapter 7 Image Sensor Camera Interface LVDS Camera Interface 51 Camera Interface Signals 51 Ch...

Page 5: ...UG235 v1 2 1 October 31 2007 www xilinx com Video Input Output Daughter Card LVDS Camera 66 ML402 Board 67 www BDTIC com XILINX ...

Page 6: ...Video Input Output Daughter Card www xilinx com UG235 v1 2 1 October 31 2007 www BDTIC com XILINX ...

Page 7: ... 3 5 Component Video Output Block Diagram 27 Chapter 4 DVI VGA Input Interface Figure 4 1 DVI Connectivity on VIODC Block Diagram 33 Figure 4 2 VGA Interface 35 Figure 4 3 Synchronization Signaling 35 Figure 4 4 Pixel Sampling 36 Figure 4 5 Ideal ADC Sampling Positions 37 Chapter 5 DVI VGA Output Interface Figure 5 1 DVI VGA Video Output Interface Block Diagram 41 Chapter 6 SDI Interface Figure 6 ...

Page 8: ...figured for VIODC Mounted to an ML402 Board 54 Appendix A Reference Information Appendix B VSK I O Connector Location Pictures Figure B 1 VIODC Rear View 63 Figure B 2 VIODC Left Side View 64 Figure B 3 VIODC Right Side View 65 Figure B 4 LVDS Camera 66 Figure B 5 ML402 Board 67 Figure B 6 ML402 Evaluation Platform 68 www BDTIC com XILINX ...

Page 9: ...I VGA Output Interface Table 5 1 Configuration Modes for TPF410 I2C Video Encoder Chip 42 Chapter 6 SDI Interface Table 6 1 RocketIO Reference Clock Generation 44 Table 6 2 ADV7321B Register Settings for HD 46 Table 6 3 ADV7321B HD Mode Register 1 0x10 Settings by Video Format 47 Table 6 4 ADV7321B Register Settings for NTSC 47 Table 6 5 ADV7321B Register Settings for PAL 47 Chapter 7 Image Sensor...

Page 10: ...Video Input Output Daughter Card www xilinx com UG235 v1 2 1 October 31 2007 Appendix B VSK I O Connector Location Pictures www BDTIC com XILINX ...

Page 11: ... the VGA and DVI input interface Chapter 5 DVI VGA Output Interface provides an overview of the VGA and DVI output interface Chapter 6 SDI Interface provides an overview of the SDI video interface Chapter 7 Image Sensor Camera Interface describes the Irvine Sensors LVDS RGB camera interface Chapter 8 Attaching the VIODC to the ML40x Development Board provides information necessary for proper attac...

Page 12: ...lic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are requ...

Page 13: ...Example Blue text Cross reference link to a location in the current document See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Red text Cross reference link to a location in another document See Figure 2 5 in the Handbook Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files www BDTIC com XILINX ...

Page 14: ...14 www xilinx com Video Input Output Daughter Card UG235 v1 2 1 October 31 2007 Preface About This Guide R www BDTIC com XILINX ...

Page 15: ...s computer graphics video interfaces such as VGA over DVI and SDI interfaces Figure 1 2 shows a block diagram of the VIODC card The VIODC consists of a number of video interface ICs connected to a Xilinx XCV2P7 FPGA The VIODC is a daughter card which plugs onto a Xilinx ML40x FPGA platform via the XGI connector The XGI connector provides a 64 signal bus between the ML40x and the VIODC Collectively...

Page 16: ...component video input on the supports 1080I 720P and 525P video standards The Component video interface devices on the VSK support 10 bit digital video Component video input is supported by the ADV7403 IC decoder IC and output by the ADV7321 encoder IC and analog filter sections DVI Digital Video I O The VSK supports DVI video inputs and outputs DVI is commonly used to interface to flat panel disp...

Page 17: ...e used on XiIinx ML40x FPGA development platforms The XGI connector is used to connect to the VIODC to a standard FPGA development platform such as the ML402 The signals consist of 32 single ended LVCMOS25 signals and 32 signals that can be configured as either 32 LVCMOS25 signals or 16 LVDS signal pairs The LVDS pairs are length matched and routed as pairs on the PCB In addition 5V power is passe...

Page 18: ...18 www xilinx com Video Input Output Daughter Card UG235 v1 2 1 October 31 2007 Chapter 1 VIODC Overview R www BDTIC com XILINX ...

Page 19: ... an I2C bus an industry standard 2 pin serial data bus used to communicate and configure ICs to access registers on the VIODC video interface FPGA VIOBUS Clocking The VIOBUS uses a simple synchronous interface running at 100 MHz Figure 2 1 A clock is passed from the ML402 FPGA to the VIODC using differential signaling All data signals are single ended The VIODC transmits data back to the ML402 FPG...

Page 20: ...n_ena Pixel enable for vio_up 25 0 1 LVCMOS25 100 MHz VIODC hdr1 44 Sport Serial Bus used to configure registers in the VIODC FPGA vio_sport_up Sport write data 16 bit data 16 bit address 1 LVCMOS25 10 MHz ML402 hdr1 54 vio_sport_dn Sportreturndata 1 LVCMOS25 10 MHz VIODC hdr1 52 vio_sport_sync Sport sync pulse 1 LVCMOS25 10 MHz ML402 hdr1 50 vio_sport_clk Sport clock 1 LVCMOS25 10 MHz ML402 hdr1 ...

Page 21: ...r an I2C control serial bus for control and ancillary data ADV7403 Video Decoder The ADV7403 is a high quality single chip multiple format video decoder and graphics digitizer This multiple format decoder automatically supports the conversion of PAL NTSC and SECAM standards in the form of composite or S video into a digital ITU R BT 656 format The component processor is capable of decoding digitiz...

Page 22: ...nsfer in a multiplexed fashion the digital video data stream into the device The Y and C buses would not be used Refer to Analog Devices ADV7321 data sheet for further details Video Signal Input and Output Conditioning Each of the video input and output signals must be conditioned to ensure that the physical interfaces meet impedance and electrical specification for each individual video standard ...

Page 23: ...18 19 27 4 5 21 29 28 30 11 22 71 52 20 23 24 12 13 14 15 1 8 31 6 10 2 3 U24 VID_OUT_Y_GRN VID_OUT_PB_BLU VID_IN_Y_GRN_I VID_IN_PB_BLU_I VID_IN_PR_RED_I 1 2 R28 75R ERJ2RKF75R0X PANASONIC 2 1 R31 75R PANASONIC ERJ2RKF75R0X 1 2 C6 ECE V0JA221WP ELEC 10 1 2 C7 ECE V0JA221WP ELEC 10 2 1 R32 75R PANASONIC ERJ2RKF75R0X VID_IN_PR_RED VID_IN_Y_GRN VID_IN_PB_BLU VID_IN_COMPOS VID_IN_LUMA VID_IN_CHROMA VI...

Page 24: ...he digital video data stream and information needed to convert to generate analog S Video Y C signals The FPGA writes the digital video data stream and control into the ADV7321 which then produces the appropriate analog output with complete video timing The format of the data written is selectable the analog output is first conditioned and then placed on the output S Video connector J20 S Video Ou...

Page 25: ... digital converter and automatic format detection logic to generate the digital video data stream Configuration of the ADV7403 device is through the I2C control bus and appropriate writes to a number of registers As part of the configuration process the user will select the format of the output data For programming details please refer to the Analog Devices ADV7403 data sheet Composite Video Outpu...

Page 26: ...ntrol and I2C control busses Figure 3 3 illustrates the VIODC composite video input configuration through ADV7403 video decoder to Xilinx XC2VP4 FPGA Input Signal Conditioning The three RCA jacks X1 X3 and X5 are color coded Red Green and Blue respectively and form the physical connectors for the component video inputs Conditioning of the analog input signal is done using circuit detailed in Figur...

Page 27: ...ock diagram of the component video output system on the VIODC board FPGA to ADV7321 Connection The Xilinx XC2VP4 FPGA drives digital video data streams in either standard and or high definition video format onto three separate 10 bit wide digital input ports of the ADV7321 For all supported standards the ADV7321 generates all horizontal vertical and blanking signals Six high performance 12 bit dig...

Page 28: ...iguring the ADV7403 device The ADV7403 is mapped to I2C address 0x40 0x41 Table 3 1 Configuration Modes for ADV7403 Video Decoder Chip Register Name Register Address Register Value Description 525P Primary Mode 0x05 0x01 Video Standard 0x06 0x08 2 0 PRIM_MODE Enable XTAL 0x1D 0x47 3 0 VID_STD ADC Power and PLL 0x3a 0x10 latch clock 13 55 MHz Bias Control 0x3b 0x80 External Bias Enable TLLC Control...

Page 29: ...30 bit 0x85 0x18 Turn off SSPD as sync is on Y 0x86 0x0b ENABLE SDTI line count mode 0xb3 0xfe SDTI ADC sw1 0xc3 0x54 7 4 adc1 3 0 adc0 ADC sw2 0xc4 0x86 7 sw_en 6 SOG 3 0 adc2 0x0e 0x80 Startup sequence 0x52 0x46 0x54 0x00 0x0e 0x00 1080I Primary Mode 0x05 0x01 Video Standard 0x06 0x0c 2 0 PRIM_MODE Enable XTAL 0x1D 0x47 3 0 VID_STD ADC power and PLL 0x3a 0x21 Latch clock Bias Control 0x3b 0x80 E...

Page 30: ...18 Turn off SSPD as sync is on Y 0x86 0x0b ENABLE SDTI line count mode 0xb3 0xfe SDTI ADC sw1 0xc3 0x54 7 4 adc1 3 0 adc0 ADC sw2 0xc4 0x86 7 sw_en 6 SOG 3 0 adc2 0x0e 0x80 Startup sequence 0x52 0x46 0x54 0x00 0x0e 0x00 Notes 1 The ADC sw1 and sw2 are unique to the VIODC input configuration Table 3 1 Configuration Modes for ADV7403 Video Decoder Chip Continued Register Name Register Address Regist...

Page 31: ... sync_mode 0 hvsync 1 EAVcodes2 async 1 0 output_levels HD Mode Reg 2 0x11 0x01 3 tp_Field_en 2 test_pattern_on 0 data_valid_en HD Mode Reg 4 0x13 0x04 7 dbuf 6 4 2 2 4 4 4 5 SSAF 3 sync_filter 2 10 bit 0 crcb HD Mode Reg 6 0x15 0x00 7 6 filter 5 gamma_en 4 gamma_a b 3 dac_swap 2 syncPrPb 1 rgb_input 525PS Power Mode 0x00 0xFE Input Mode 0x01 0x20 Mode 0x02 0x30 HD Mode Reg 1 0x10 0x00 HD Mode Reg...

Page 32: ...Input Mode 0x01 0x20 Mode 0x02 0x30 HD Mode Reg 1 0x10 0x20 HD Mode Reg 2 0x11 0x01 HD Mode Reg 4 0x13 0x24 HD Mode Reg 6 0x15 0x00 10801 Power Mode 0x00 0xFE Input Mode 0x01 0x20 Mode 0x02 0x30 HD Mode Reg 1 0x10 0x68 HD Mode Reg 2 0x11 0x01 HD Mode Reg 4 0x13 0x04 HD Mode Reg 6 0x15 0x00 Table 3 2 Configuration Modes for ADV7321A Video Encoder Chip Continued Register Name Register Address Regist...

Page 33: ...ors The second connector is a DVI I connector which includes pins for both the analog VGA interface and the DVI digital interface Note that the analog pins of the two connectors are tied together so that only one or the other can be used at any time See Figure 4 1 VIODC uses Analog Devices AD9887A dual interface for flat panel displays This part includes two very separate subsections the analog VG...

Page 34: ...VI connector for negotiating encryption keys when High bandwidth Digital Content Protection HDCP is required The AD9887A interface supports this functionality and has an EEPROM for storing these keys AD9887 Overview The AD9887A dual interface includes both analog and digital interfaces Refer to the AD9887A interface data sheet for further details Analog Interface The AD9887A is a complete 8 bit 17...

Page 35: ...s The video data is carried by three 75Ω transmission lines coax one each for red green and blue When 75Ω terminated at the monitor the voltage typically ranges from 0 mV 700 mV This voltage indicates 0 100 intensity on the associated color In a CRT these voltages adjust the intensity of the electron beam for each color Synchronization signaling is used to control the scanning of the electron beam...

Page 36: ... to operate properly it must sample each pixel at the appropriate time Figure 4 4 To explain VGA sampling theory it is useful to use a greatly simplified example Figure 4 4 shows a single line from a frame with the horizontal front porch set to 1 the sync length set to 1 and the horizontal back porch set to 2 The line has 12 active pixels In order to receive the video data these are the only signa...

Page 37: ...put signal resulting in an input signal reference to ground For this circuit to function properly this clamp should only be enabled when the input data is known to be black such as during the horizontal back porch The AD9887A has a clamp placement register to control the start of the clamp in cycles after the falling edge of HSYNC The clamp duration register controls the length of the clamp in cyc...

Page 38: ...oding scheme results in 10 bit symbols for each 8 bit byte thus the encoded bit rate is 10x the byte rate Each pixel is encoded as a 24 bit value 8 bits for each color Just like VGA each color is transferred separately so each color has its own differential pair This means that the encoded bit rate is 10x the pixel rate DVI also requires a separate clock reference signal increasing the number of d...

Page 39: ...gister Value Description Active Interface 0x12 0x81 Force selection of analog input PLL Div MSB 0x01 0x69 PLL divider value SXGA60 has 1688 cycles per HSYNC period 1688 1 0x697 PLL Div LSB 0x02 0x70 VCO CPMP 0x03 0xD0 VCORNGE 10 CURRENT 100 Phase Adjust 0x04 0x80 Default phase T 2 Clamp Placement 0x05 0x64 100 cycles after HSYNC Clamp Duration 0x06 0x64 100 cycles in duration HSOUT Pulse width 0x0...

Page 40: ...tion at http www vesa org DVI specifications are freely available from the Digital Display Working Group at http www ddwg org Clamp Duration 0x06 0x78 120 cycles in duration HSOUT Pulse width 0x07 0xC0 192 cycles in HSYNC Table 4 5 Analog UXGA60 Continued Register Name Register Address Register Value Description Table 4 6 DVI Register Name Register Address Register Value Description Active Interfa...

Page 41: ...l video bus carrying RGB data HSYNC and VSYNC Independent pixel clocks are routed the devices The triple DAC supports 10 bit channel RGB video DVI interface supports only 8 bit channel video and the video data ports are connected to the 8 MSBs of the video data bus The DVI interface also requires a data enable to distinguish active video from inactive video pixels The TPF410 is configured via as I...

Page 42: ...e is initialized with a single write of 0x3f to location 0x08 The DVI I2C interface is mapped to location 0x70 0x71 Table 5 1 Configuration Modes for TPF410 I2C Video Encoder Chip Register Name Register Address Register Value Description ctl_1_mode 0x08 0x3F 5 vsyc_enable 4 hsyc_enable 3 dontcare 2 24 bit operation 1 posedge 0 powerup www BDTIC com XILINX ...

Page 43: ... by the SDI receiver into analog video A PicoBlaze processor is used to control the ADV7321B video encoder through the I2C interface The PicoBlaze processor code includes an interactive debugger allowing registers in the ADV7321B to be read or written through a ChipScope video input and output VIO console Reference Clocks The source of reference clocks for the SDI transmitter and receiver is a com...

Page 44: ... receiver locks 1 It is possible to use 108 MHz instead of 54 MHz for SD SDI in the transmitter However because the ICS664 02 cannot directly generate 108 MHz a DCM would be required to generate the 108 MHz clock resulting in more jitter on the output of the SDI transmitter due to higher jitter on the reference clock The receiver section requires 108 MHz and cannot get by with 54 MHz However jitte...

Page 45: ...ate eight times faster than the 270 Mb s bit rate The RXRECCLK output clock from the RocketIO receiver is equal in frequency to the reference clock 108 MHz and is not a true recovered clock The RocketIO receiver outputs 20 bits of 8X oversampled data every cycle of RXRECCLK The oversampled data from the RocketIO receiver goes into a data recovery unit This unit examines the oversampled data and re...

Page 46: ...the Write Data field then click on the Write Strobe button The debugger will always do a read of the register after it is written and display the updated value in the Read Data field Table 6 2 lists the settings of the ADV7321B registers when running in HD mode Register 10 varies depending on the video format and is listed separately in Table 6 3 Table 6 4 lists the settings used when the running ...

Page 47: ...40 0x10 Select NTSC format SD mode 1 0x42 0x40 SD pixel data valid SD mode 3 0x44 0x00 Colorbars off SD mode 6 0x48 0x10 10 bit input SD timing 0 0x4A 0x08 SD timing mode 0 and blank disabled SD Fsc 0 0x4C 0x16 SD Fsc 1 0x4D 0x7c SD Fsc 2 0x4E 0xF0 SD Fsc 3 0x4F 0x21 Table 6 5 ADV7321B Register Settings for PAL Register Name Address Value Description Power mode 0x00 0xFC Enable DACs Mode select 0x...

Page 48: ...RocketIO transceiver where it is serialized and sent as an HD SDI bitstream In SD mode the clock from the ICS664 02 runs at 54 MHz This is supplied to the RocketIO transceiver where it is multiplied by 20 so that the actual data rate of the transceiver s output is 1 08 Gb s or 4X the 270 Mb s SD SDI bit rate The SD pattern generator and the other elements of the SD SDI transmitter data path need t...

Page 49: ...t four identical bits are fed to the RocketIO transmitter s data port for each encoded bit This effectively slows the bit rate of the transmitter down to 270 Mb s References 1 Xilinx application note XAPP683 Multi Rate HD SD SDI Transmitter Using Virtex II Pro RocketIO Multi Gigabit Transceivers 2 Xilinx application note XAPP684 Multi Rate HD SD SDI Receiver Using Virtex II Pro RocketIO Multi Giga...

Page 50: ...50 www xilinx com Video Input Output Daughter Card UG235 v1 2 1 October 31 2007 Chapter 6 SDI Interface R www BDTIC com XILINX ...

Page 51: ...rface is not compatible with Ethernet Camera Interface Signals The camera interface signals are shown in Table 7 1 The LVDS camera Figure 7 2 is available with a monochrome or RGB image sensor The interface consists of a clock pair which runs at 12X the pixel rate The pixel rate is 26 xx Figure 7 1 LVDS Camera Interface VIODC RJ45 Connect Cat 6 Cable RGB ug235_ch6_01_120805 Table 7 1 Camera Interf...

Page 52: ...h HSYNC and VSYNC encoded into the video data Refer to the Micron MT9V022 data sheet for more details on configuration modes The timing relationship between the clock and data is not specified nor is the maximum cable rate This requires the FPGA receiver to have the ability to adjust or skew the camera clock phase to clock in valid camera data This is shown in Figure 7 1 Figure 7 2 Camera Clock XC...

Page 53: ...veral jumpers are required to be configured properly for correct operation The required jumper positions are detailed in Table 8 1 and shown in Figure 8 1 and Figure 8 2 Table 8 1 Required Jumper Positions Function Jumper Board VIODC Standalone ML402 Standalone VIODC ML40X VIODC 5V Power J13 VIODC to Back Pins 1 2 to Front Pins 2 3 Bank 7 Voltage J16 ML40x Front 3 3V Pins 1 2 Back 2 5V Pins 1 2 JT...

Page 54: ...for VIODC Mounted to an ML402 Board TDO EXP Pin 2 3 Back VIODC ML402 Pin 1 2 Front ML402 J16 Pin 2 3 Back VIODC ML402 Pin 1 2 Front ML402 ug235_ch8_011606 Figure 8 2 Configuration Jumper Locations on the VIODC Top Configured for VIODC Mounted to an ML402 Board UG235_CH8_02_011606 ML402 MOTHERBOARD VIDEO IO DAUGHTER CARD J12 Pin 2 3 Front VIODC ML402 Pin 1 2 Back VIODC Jack 1 VIODC 5V Power Jack ww...

Page 55: ...V7403A ADV7403A ANALOG_DEVICES ADV7123JST330 330 MHz Triple 10 Bit High Speed Video DAC ADV7123 ADV7123 GENNUM GS1524 CKD Multi Rate SDI Adaptive Cable Equalizer GS1524 GS1524 GENNUM GS1528 CKA Multi Rate SDI Dual Slew Rate Cable Driver GS1528 GS1528 ICS ICS1523MLFT Video Clock Synthesizer with I C Programmable Delay CS1523 CS1523 ICS ICS664G 02LFTR PECL Digital Video Clock Source CS664 CS66402 MA...

Page 56: ...18 Y23 A8 vio_up9 vio_up_lvds4_P hdr2 20 Y22 B8 vio_up10 vio_up_lvds5_N hdr2 22 AA20 G14 vio_up11 vio_up_lvds5_P hdr2 24 AA19 F14 vio_up12 vio_up_lvds6_N hdr2 26 AA17 H15 vio_up13 vio_up_lvds6_P hdr2 28 Y17 H14 vio_up14 vio_up_lvds7_N hdr2 30 AC20 F15 vio_up15 vio_up_lvds7_P hdr2 32 AB20 E15 vio_dn0 vio_dn_lvds0_N hdr2 34 AD21 D15 vio_dn1 vio_dn_lvds0_P hdr2 36 AE21 C15 vio_dn2 vio_dn_lvds1_N hdr2...

Page 57: ...8 vio_dn17 vio_dn1 hdr1 26 AA23 AF19 vio_dn18 vio_dn2 hdr1 28 AC21 AE19 vio_dn19 vio_dn3 hdr1 30 AB26 AD15 vio_dn20 vio_dn4 hdr1 32 AC23 AC15 vio_dn21 vio_dn5 hdr1 34 AB25 AD19 vio_dn22 vio_dn6 hdr1 36 AD23 AB15 vio_dn23 vio_dn7 hdr1 38 AC26 AA15 vio_dn24 vio_dn8 hdr1 40 AD26 W15 vio_dn25 vio_dn9 hdr1 42 AC22 Y14 vio_dn_clk_ena vio_dn_clk_ena hdr1 44 V22 AC14 vio_reset vio_reset hdr1 46 V21 AB14 v...

Page 58: ...Y21 HDR2_18 vio_up5 vio_up_lvds2_P IO_L20P_7_Y20 Y20 HDR2_20 vio_up6 vio_up_lvds3_N IO_L4N_VREF_7_W24 W24 HDR2_10 vio_up7 vio_up_lvds3_P IO_L4P_7_W23 W23 HDR2_12 vio_up8 vio_up_lvds4_N IO_L12N_VREF_7_Y23 Y23 HDR2_6 vio_up9 vio_up_lvds4_P IO_L12P_7_Y22 Y22 HDR2_8 vio_up10 vio_up_lvds5_N IO_L26N_SM2_7_AA20 AA20 HDR2_58_SYS_MON_VN2 vio_up11 vio_up_lvds5_P IO_L26P_SM2_7_AA19 AA19 HDR2_60_SYS_MON_VP2 v...

Page 59: ...W25 W25 HDR1_52 vio_up21 vio_up5 IO_L7P_7_AB24 AB24 HDR1_32 vio_up22 vio_up6 IO_L8N_CC_LC_7_Y24 Y24 HDR1_26 vio_up23 vio_up7 IO_L14P_7_AB23 AB23 HDR1_12 vio_up24 vio_up8 IO_L2N_7_W26 W26 HDR1_50 vio_up25 vio_up9 IO_L6N_7_Y26 Y26 HDR1_38 vio_up_clk_ena vio_up_clk_ena IO_L6P_7_Y25 Y25 HDR1_40 vio_dn16 vio_dn0 IO_L10N_7_AA26 AA26 HDR1_22 vio_dn17 vio_dn1 IO_L14N_7_AA23 AA23 HDR1_10 vio_dn18 vio_dn2 I...

Page 60: ...gle Ended Mode Signal Name VIOBUS Differential Mode Signal Name VIODC XCV2P4 FPGA Pin Name Pin VIODC Schematic Signal Name vio_up0 vio_up_lvds0_N IO_L01N_1 VRP_1_A3 A3 V4_IOB_L21_N vio_up1 vio_up_lvds0_P IO_L01P_1 VRN_1_B3 B3 V4_IOB_L21_P vio_up2 vio_up_lvds1_N IO_L06N_1_E9 E9 V4_IOB_L18_N vio_up3 vio_up_lvds1_P IO_L06P_1_E8 E8 V4_IOB_L18_P vio_up4 vio_up_lvds2_N IO_L09N_1 VREF_1_F9 F9 V4_IOB_L20_...

Page 61: ...15 vio_dn_lvds7_P IO_L01P_0 VRN_0_A24 A24 V4_IOB_L31_P vio_up16 vio_up0 IO_L05_4 No_Pair_Y8 Y8 V4_IOB_L8_P_LC vio_up17 vio_up1 IO_L09N_4_Y9 Y9 V4_IOB_L5_N vio_up18 vio_up2 IO_L73N_4_Y13 Y13 V4_IOB_L9_P_LC vio_up9 vio_up3 IO_L67N_4_AA12 AA12 V4_IOB_L16_N vio_up20 vio_up4 IO_L73P_4_AA13 AA13 V4_IOB_L2_P vio_up21 vio_up5 IO_L06N_4 VRP_4_AB8 AB8 V4_IOB_L7_P vio_up22 vio_up6 IO_L06P_4 VRN_4_AB9 AB9 V4_...

Page 62: ...IOB_L3_N vio_sport_sync vio_sport_sync IO_L69P_5_W15 W15 V4_IOB_L11_N vio_sport_dn vio_sport_dn IO_L05_5 No_Pair_Y19 Y19 V4_IOB_L13_N vio_sport_up vio_sport_up IO_L06N_5 VRP_5_AB18 AB18 V4_IOB_L3_P vio_i2c_scl_up vio_i2c_scl_up IO_L09N_5 VREF_5_AA18 AA18 V4_IOB_L5_P vio_i2c_sda_dn vio_i2c_sda_dn IO_L73N_5_AA14 AA14 V4_IOB_L24_N_LC vio_i2c_sda_up vio_i2c_sda_up IO_L69N_5 VREF_5_W14 W14 V4_IOB_L15_P...

Page 63: ...235 v1 2 1 October 31 2007 R Appendix B VSK I O Connector Location Pictures VIODC Connectors Figure B 1 VIODC Rear View LVDS Camera Power Switch 5V Power Input ML402 ML402 Audio VIODC JTAG Connector ML402 Ethernet VIODC VGA In VGA Out www BDTIC com XILINX ...

Page 64: ... Video Input Output Daughter Card UG235 v1 2 1 October 31 2007 Appendix B VSK I O Connector Location Pictures R Figure B 2 VIODC Left Side View VIODC DVI In ML402 RS 232 VIODC DVI VGA Out ML402 JTAG www BDTIC com XILINX ...

Page 65: ...1 October 31 2007 VIODC Connectors R Figure B 3 VIODC Right Side View VIODC SDI Out VIODC SDI IN VIODC Composite In VIODC Composite Out VIODC Y Out VIODC Y In VIODC Pb Out VIODC Pb In VIODC Pr Out VIODC Pr In VIODC S Video In VIODC S Video In www BDTIC com XILINX ...

Page 66: ... www xilinx com Video Input Output Daughter Card UG235 v1 2 1 October 31 2007 Appendix B VSK I O Connector Location Pictures R LVDS Camera Figure B 4 LVDS Camera LVDS Camera HOST Port www BDTIC com XILINX ...

Page 67: ...Video Input Output Daughter Card www xilinx com 67 UG235 v1 2 1 October 31 2007 ML402 Board R ML402 Board Figure B 5 ML402 Board www BDTIC com XILINX ...

Page 68: ...68 www xilinx com Video Input Output Daughter Card UG235 v1 2 1 October 31 2007 Appendix B VSK I O Connector Location Pictures R Figure B 6 ML402 Evaluation Platform www BDTIC com XILINX ...

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