Xilinx SP605, Hardware User'S Manual

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UG526 (v1.9) February 14, 2019 www.xilinx.com SP605 Hardware User Guide
07/18/11 1.6 Corrected “jitter” to “stability” in section Oscillator (Differential) . Revised the feature
and notes descriptions for reference numbers 6 and 12 in Table 1-1 . Revised FPGA pin
numbers for ZIO and RZQ in Table 1-4 . Added Table 1-29 , Table 1-31 , and table notes in
Table 1-30 .
06/19/12 1.7 Removed reference to FPGA speed grade in 2. 128 MB DDR3 Component Memory .
Added IIC External Access Header . Updated SFP Module connector reference
designator in 8. Multi-Gigabit Transceivers (GTP MGTs) .
09/24/12 1.8 Updated Figure 1-2 . Added Regulatory and Compliance Information .
02/14/19 1.9 Updated the Electrostatic Discharge Caution section, Appendix C, Xilinx Design
Constraints , and Appendix D, Regulatory and Compliance Information . Updated 2. 128
MB DDR3 Component Memory .
Date Version Revision