Xilinx SP605, Hardware User'S Manual

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SP605 Hardware User Guide www.xilinx.com UG526 (v1.9) February 14, 2019
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Revision History
The following table shows the revision history for this document.
Date Version Revision
10/07/09 1.0 Initial Xilinx release.
11/09/09 1.1 • Updated Figure 1-17 and Figure 1-23 .
• Changed speed grade from -2 to -3.
• Miscellaneous typographical edits.
02/01/10 1.1.1 Minor typographical edits to Table 1-24 and Table 1-25 .
05/18/10 1.2 Updated Figure 1-2 . Added Note 6 to Table 1-11 . Updated board connections for
SFP_TX_DISABLE in Table 1-12 . Added note about FMC LPC J63 connector in 18. VITA
57.1 FMC LPC Connector . Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in
Table 1-28 . Updated description of PMBus Pod and TI Fusion Digital Power Software
GUI in Onboard Power Regulation . Updated Appendix B, VITA 57.1 FMC LPC
Connector Pinout , and Appendix C, Xilinx Design Constraints .
06/16/10 1.3 Updated 2. 128 MB DDR3 Component Memory . Added note 1 to Table 1-30 .
09/24/10 1.4 Updated description of Fusion Digital Power Software in Onboard Power Regulation .
02/16/11 1.5 Revised oscillator manufacturer information from Epson to SiTime in Table 1-1 . Revised
oscillator manufacturer information from Epson to SiTime on page page 26 . Deleted note
on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”
Revised values for R50 and R216 in
Figure 1-12 . Revised oscillator manufacturer
information from Epson to SiTime on page page 69 .