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SP605 Hardware User Guide

65

UG526 (v1.9) February 14, 2019

Appendix C

Xilinx Design Constraints

Overview

The Xilinx Design Constraints (XDC) file template provides for designs targeting the SP605
evaluation board. Net names in the constraints correlate with net names on the latest SP605
evaluation board schematic. Identify the appropriate pins and replace the net names with
net names in the user RTL.

See the

Constraints Guide

for more information.

Note:

The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V

(nonadjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are
compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

Note:

The latest version of the Xilinx constraint file can be found on the

Spartan-6 FPGA SP605

website.

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Summary of Contents for SP605

Page 1: ...SP605 Hardware User Guide UG526 v1 9 February 14 2019...

Page 2: ...rformance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed at https www xilinx com legal htm tos A...

Page 3: ...le notes in Table 1 30 06 19 12 1 7 Removed reference to FPGA speed grade in 2 128 MB DDR3 Component Memory Added IIC External Access Header Updated SFP Module connector reference designator in 8 Mult...

Page 4: ...SP605 Hardware User Guide www xilinx com UG526 v1 9 February 14 2019...

Page 5: ...4 Linear BPI Flash 21 FPGA Design Considerations for the Configuration Flash 23 5 System ACE CF and CompactFlash Connector 23 6 USB JTAG 25 7 Clock Generation 26 Oscillator Differential 26 Oscillator...

Page 6: ...Mode DIP Switch SW1 Active High 52 18 VITA 57 1 FMC LPC Connector 53 19 Power Management 55 AC Adapter and 12V Input Power Jack Switch 55 Onboard Power Regulation 57 Configuration Options 60 Appendix...

Page 7: ...tan 6 Family Overview This overview outlines the features and product selection of the Spartan 6 family Spartan 6 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and s...

Page 8: ...itecture of the DSP48A1 slice in Spartan 6 FPGAs and provides configuration examples Spartan 6 FPGA Memory Controller User Guide This guide describes the Spartan 6 FPGA memory controller block a dedic...

Page 9: ...Information Additional information and support material is located at Spartan 6 FPGA SP605 Evaluation Kit This information includes Current version of this user guide in PDF format Example design fil...

Page 10: ...l Socket with a 2 5V 27MHz oscillator single ended SMA connectors differential SMA connectors for MGT clocking differential 8 Multi Gigabit Transceivers GTP MGTs FMC LPC connector SMA PCIe SFP module...

Page 11: ...f the SP605 and its peripherals X Ref Target Figure 1 1 Figure 1 1 SP605 Features and Banking Spartan 6 XC6SLX45T 3FGG484 U1 PCIe 125 MHz Clk SMA REFCLK SFPCLK FMC GBTCLK Bank 0 2 5V Bank 1 2 5V Bank...

Page 12: ...ent failures Always follow ESD prevention procedures when removing and replacing components To prevent ESD damage Use an ESD wrist or ankle strap and ensure that it makes skin contact Connect the equi...

Page 13: ...re 1 2 SP605 Board 15e 13 16b 19 7a 15h 1 2 3 4 8 15g 5 17c 9 3 14 on back side 7b 10 18 6 12 16c 11 17b 15b 15a 17a 19b 15d UG526_02 _092412 15c 8 7c 16d 17d 16a 15f Table 1 1 SP605 Features Number F...

Page 14: ...le Cage Connector AMP 136073 1 12 11 Ethernet 10 100 1000 Marvell M88E1111 EPHY 11 12 USB JTAG Conn USB Mini B USB JTAG Download Circuit 15 13 DVI Codec and Video Connector Chrontel CH7301C TF 16 17 1...

Page 15: ...uring the FPGA see Configuration Options Mode switch SW1 see Table 1 32 is set to 10 Slave SelectMAP to choose the System ACE CF default configuration See the Spartan 6 FPGA Configuration User Guide U...

Page 16: ...s 16 bit data path using SSTL15 signaling Manufacturer Micron Part Number MT41J64M16LA 187E Description 1 Gb 128 MB 64 Mb x 16 1 5V 96 ball FBGA Performance up to DDR3 1066 The SP605 board supports th...

Page 17: ...nts U1 FPGA Pin FPGA Pin Number Board Connection for OCT ZIO M7 No Connect RZQ K7 100 to GROUND Table 1 5 DDR3 Component Memory Connections U1 FPGA Pin Schematic Net Name Memory U42 Pin Number Pin Nam...

Page 18: ...DQ11 D7 DQ8 W3 MEM1_DQ12 A3 DQ15 W1 MEM1_DQ13 C8 DQ10 Y2 MEM1_DQ14 B8 DQ14 Y1 MEM1_DQ15 A7 DQ12 H2 MEM1_WE_B L3 WE_B M5 MEM1_RAS_B J3 RAS_B M4 MEM1_CAS_B K3 CAS_B L6 MEM1_ODT K1 ODT K4 MEM1_CLK_P J7 C...

Page 19: ...a 2 5V bank The XC6SLX45T 3FGG484 is a master device when accessing an external SPI flash memory device The SP605 SPI interface has two parallel connected configuration options Figure 1 3 an SPI X4 W...

Page 20: ...ns U1 FPGA Pin Schematic Net Name SPI MEM U32 SPI HDR J17 Pin Pin Name Pin Pin Name AB2 FPGA_PROG_B 1 T14 FPGA_D2_MISO3 1 IO3_HOLD_B 2 R13 FPGA_D1_MISO2_R 9 IO2_WP_B 3 AA3 SPI_CS_B 4 TMS AB20 FPGA_MOS...

Page 21: ...tions X Ref Target Figure 1 5 Figure 1 5 Linear BPI Flash Interface Table 1 7 Linear Flash Connections U1 FPGA Pin Schematic Net Name U25 BPI FLASH Pin Number Pin Name N22 FLASH_A0 29 A1 N20 FLASH_A1...

Page 22: ...AA6 FLASH_D3 41 DQ3 AB6 FLASH_D4 47 DQ4 Y5 FLASH_D5 49 DQ5 AB5 FLASH_D6 51 DQ6 W9 FLASH_D7 53 DQ7 T7 FLASH_D8 35 DQ8 U6 FLASH_D9 37 DQ9 AB19 FLASH_D10 40 DQ10 AA18 FLASH_D11 42 DQ11 AB18 FLASH_D12 48...

Page 23: ...rts up to eight configuration images on a single CompactFlash card The configuration address switches allow the user to choose which of the eight configuration images to use The CompactFlash CF card s...

Page 24: ...if a Compact Flash CF card is installed in the CF socket U37 the System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1 Every time a Co...

Page 25: ...able JTAG access to the FPGA on the basic SP605 board without FMC expansion modules installed AA1 SYSACE_MPBRDY 39 MPBRDY W4 SYSACE_MPCE 42 MPCE AA2 SYSACE_MPIRQ 41 MPIRQ T6 SYSACE_MPOE 77 MPOE T5 SYS...

Page 26: ...the USB J4 connection iMPACT can download a temporary design to the FPGA through the JTAG This provides a connection within the FPGA from the FPGAs JTAG port to the FPGAs BPI interface Through the con...

Page 27: ...tor installed Figure 1 8 shows the unpopulated user oscillator socket This figure indicates the socket pin 1 location Figure 1 9 shows the oscillator installed with its pin 1 location identifiers X Re...

Page 28: ...ndpoint P4 edge connector fingers One 1 MGT is wired to the FMC LPC connector J2 One 1 MGT is wired to MGT SMA connectors J36 J37 One 1 MGT is wired to the SFP Module connector P2 The SP605 includes a...

Page 29: ...D3 GND4 GND5 GND6 GND7 SIG GND1 GND2 GND3 GND4 GND5 GND6 GND7 SIG SMA MGT Connectors MGT REFCLK 2 3 4 5 6 7 8 1 J35 32K10K 400E3 2 3 4 5 6 7 8 1 32K10K 400E3 J34 1 8 7 6 5 4 3 2 32K10K 400E3 J36 SMA_R...

Page 30: ...v1 9 February 14 2019 Chapter 1 SP605 Evaluation Board Table 1 10 GTP SMA Clock Connections U1 FPGA Pin Schematic Net Name SMA Pin C9 SMA_RX_N J35 1 D9 SMA_RX_P J34 1 A8 SMA_TX_N J33 1 B8 SMA_TX_P J3...

Page 31: ...e better than 10 SP605 power slide switch SW2 turns the board on and off by controlling the 12V supply to the board Caution Never apply power to the power brick 6 pin Mini Fit type connector J18 and t...

Page 32: ...ers of the potential hazard See the Spartan 6 FPGA GTP Transceivers User Guide UG386 for more information Ref 6 Also see the following websites for more information about the Spartan 6 FPGA Integrated...

Page 33: ...and Status SFP Control Status Signal Board Connection SFP_TX_FAULT Test Point J15 High Fault Low Normal Operation SFP_TX_DISABLE Jumper J44 On SFP Enabled Off SFP Disabled SFP_MOD_DETECT Test Point J1...

Page 34: ...ble 1 15 shows the connections and pin numbers for the PHY Table 1 14 PHY Configuration Pins Pin Connection on Board Bit 2 Definition and Value Bit 1 Definition and Value Bit 0 Definition and Value CF...

Page 35: ...38 Ref 7 for more information U22 PHY_RXD7 120 RXD7 AB7 PHY_TXC_GTPCLK 14 GTXCLK L20 PHY_TXCLK 10 TXCLK U8 PHY_TXER 13 TXER T8 PHY_TXCTL_TXEN 16 TXEN U10 PHY_TXD0 18 TXD0 T10 PHY_TXD1 19 TXD1 AB8 PHY_...

Page 36: ...be installed on the host PC prior to establishing communications with the SP605 Refer to the evaluation kit Getting Started Guide for driver installation instructions Refer to the Silicon Labs website...

Page 37: ...01C is controlled by way of the video IIC bus The DVI connector Table 1 18 supports the IIC protocol to allow the board to read the monitor s configuration parameters These parameters can be read by t...

Page 38: ...two items FPGA U1 Bank 0 SFP IIC interface SFP module connector P2 The SP605 IIC bus topology is shown in Figure 1 11 X Ref Target Figure 1 11 Figure 1 11 IIC Bus Topology U1 P3 U31 BANK 1 IIC_SDA_MA...

Page 39: ...Netname Connected To Level Shifted Connection Level Shifted Net Name R22 IIC_SDA_MAIN J2 C31 U4 5 1 T21 IIC_SCL_MAIN J2 C30 U4 6 1 AA4 IIC_SDA_DVI Q8 2 U31 14 Q8 3 P3 7 IIC_SDA_DVI_F W13 IIC_SCL_DVI Q...

Page 40: ...Ref 21 In addition see the Xilinx XPS IIC Bus Interface Data Sheet DS606 Ref 8 Table 1 20 IIC Memory Connections U1 FPGA Pin Schematic Netname IIC Memory U4 Pin Number Pin Name Not Applicable Tied to...

Page 41: ...IO_LED_1 DS5 GPIO_LED_2 Green GPIO_LED_2 DS6 GPIO_LED_3 Green GPIO_LED_3 DS7 FPGA_AWAKE Green FPGA AWAKE DS8 SYSACE_STAT_LED Green System ACE CF Status LED System ACE CF Status DS9 TI_PWRGOOD AND MGT_...

Page 42: ...o make them visible on the connector end of the board when the SP605 board is installed into a PC motherboard This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P1 X Ref Target F...

Page 43: ...2 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured X Ref Target Figure 1 14 Figure 1 14 FPGA INIT and DONE LEDs Table 1 22 FPGA INIT and DONE LED...

Page 44: ...es four active High green LEDs as described in Figure 1 15 and Table 1 23 X Ref Target Figure 1 15 Figure 1 15 User LEDs Table 1 23 User LED Connections U1 FPGA Pin Schematic Net Name Controlled LED D...

Page 45: ...pushbuttons are assigned as GPIO and the fifth is assigned as a CPU_RESET Figure 1 16 and Table 1 24 describe the pushbutton switches X Ref Target Figure 1 16 Figure 1 16 User Pushbutton Switch Typica...

Page 46: ...is pulled up to 1 5V when closed X Ref Target Figure 1 17 Figure 1 17 User DIP Switch S2 Table 1 25 User DIP Switch Connections U1 FPGA Pin Schematic Net Name DIP Switch Pin C18 GPIO_SWITCH_0 S2 1 Y6...

Page 47: ...6W 200 R283 TXB0108 VCCB B1 B2 B3 B4 B6 B7 GND A3 A8 OE A4 A5 A7 A6 B5 A1 A2 B8 VCCA VCC1V5_FPGA VCC3V3 GPIO_HEADER_0 GPIO_HEADER_1 GPIO_HEADER_2 GPIO_HEADER_3 GPIO_HEADER_0_LS GPIO_HEADER_1_LS NC NC...

Page 48: ...re 1 19 and Table 1 27 X Ref Target Figure 1 19 Figure 1 19 User SMA GPIO Table 1 27 User SMA Connections U1 FPGA Pin Schematic Net Name GPIO SMA Pin A3 USER_SMA_GPIO_N J39 1 B3 USER_SMA_GPIO_P J40 1...

Page 49: ...gure 1 20 Power On Off Slide Switch SW2 UG526_20 _100609 N C 12v 12v N C COM COM 1 4 2 3 6 1 2 3 4 5 NC NC 39 30 1060 ATX Peripheral Cable Connector can plug into J27 when SP605 is in PC and the desk...

Page 50: ...en the System ACE CF configuration mode pin is high enabled by closing DIP switch S1 switch 4 the System ACE CF controller configures the FPGA from the CompactFlash card when a card is inserted or the...

Page 51: ...ystem ACE CF controller to configure the FPGA from the CompactFlash card when a card is inserted or the SYSACE RESET button is pressed See 5 System ACE CF and CompactFlash Connector for more details X...

Page 52: ...own in Figure 1 24 and Table 1 32 For more information refer to the Spartan 6 FPGA Configuration User Guide UG380 Ref 2 See Table 1 32 for the configuration modes X Ref Target Figure 1 24 Figure 1 24...

Page 53: ...h versions The HPC version is fully populated with 400 pins present and the LPC version is partially populated with 160 pins The 10 x 40 rows of a FMC LPC connector provides connectivity for 68 single...

Page 54: ...LA10_P H10 D14 FMC_LA09_P F7 C15 FMC_LA10_N H11 D15 FMC_LA09_N F8 C18 FMC_LA14_P C17 D17 FMC_LA13_P G16 C19 FMC_LA14_N A17 D18 FMC_LA13_N F17 C22 FMC_LA18_CC_P T12 D20 FMC_LA17_CC_P Y11 C23 FMC_LA18_C...

Page 55: ...1 FMC_LA20_P R9 H20 FMC_LA15_N D19 G22 FMC_LA20_N R8 H22 FMC_LA19_P R11 G24 FMC_LA22_P V7 H23 FMC_LA19_N T11 G25 FMC_LA22_N W8 H25 FMC_LA21_P V11 G27 FMC_LA25_P W14 H26 FMC_LA21_N W11 G28 FMC_LA25_N Y...

Page 56: ...pin connector has a different pinout than SP605 J18 and connecting the ATX 6 pin connector will damage the SP605 and void the board warranty Caution DO NOT apply power to 6 pin Mini Fit type connecto...

Page 57: ...5V 10A max PTD08A010W Linear Regulator U51 MGT AVCC 1 2V 3A max TPS74401 Sink Source Regulator U11 0 75 VTT VREF 3A max TPS51200DRCT Power Controller 1 U26 UCD9240PFC PWR Switching Module U18 Switchi...

Page 58: ...R 0 75 31 TPS51200DRCT U11 10 mA Tracking Reference output VTTVREF 0 75 31 TL1963 18DCQR U44 1 5A 2 5V IN 1 8V OUT Linear Regulator VCC1V8 1 80 31 LT1763CS8 U49 500 mA 5V IN 3 0V OUT Linear Regulator...

Page 59: ...esigner software package which includes several tools capable of communicating with the UCD92xx series of controllers from a Windows based host computer via the PMBus pod The SP605 onboard connector J...

Page 60: ...bitstream from the CF card image address pointed to by the image select switch S1 With no CF card present the SP605 can be configured via the onboard JTAG controller and USB download cable as describe...

Page 61: ...5 Table A 33 Default Switch Settings REFDES Function Type Default SW2 Board power slide switch off SW1 FPGA mode 2 pole DIP switch Slave SelectMAP default selects System ACE CF configuration 2 M1 1 on...

Page 62: ...Table A 34 Default Jumper Settings Jumper REFDES Function Default FMC JTAG Bypass J19 Exclude FMC LPC connector J2 Jump 1 2 SFP Module J22 SFP Full BW Jump 1 2 J44 SFP Enabled Jump 1 2 SPI Memory Sele...

Page 63: ...NC NC LA07_N GND NC NC LA09_P LA10_P NC NC 15 NC NC GND LA12_P NC NC LA09_N LA10_N NC NC 16 NC NC LA11_P LA12_N NC NC GND GND NC NC 17 NC NC LA11_N GND NC NC LA13_P GND NC NC 18 NC NC GND LA16_P NC N...

Page 64: ...64 www xilinx com SP605 Hardware User Guide UG526 v1 9 February 14 2019 Appendix B VITA 57 1 FMC LPC Connector Pinout...

Page 65: ...d schematic Identify the appropriate pins and replace the net names with net names in the user RTL See the Constraints Guide UG625 Ref 12 for more information Note The SP605 board VADJ voltage for the...

Page 66: ...66 www xilinx com SP605 Hardware User Guide UG526 v1 9 February 14 2019 Appendix C Xilinx Design Constraints...

Page 67: ...by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 In...

Page 68: ...stering in those countries to which Xilinx is an importer Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end of life If you have purchased...

Page 69: ...DS080 System ACE CompactFlash Solution Data Sheet 6 UG386 Spartan 6 FPGA GTP Transceivers User Guide 7 UG138 LogiCORE IP Tri Mode Ethernet MAC v4 2 User Guide 8 DS606 XPS IIC Bus Interface Data Sheet...

Page 70: ...70 www xilinx com SP605 Hardware User Guide UG526 v1 9 February 14 2019 Appendix E References...

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