Xilinx LogiCORE IP Video In to AXI4-Stream v1.0, Product Manual

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Video In to AXI4-Stream www.xilinx.com 26
PG043 April 24, 2012
Module Descriptions
The Read Logic controls the
tvalid
handshaking signal based on the level and flags from
the FIFO, and the tready signal returned from the downstream module. Whenever data is
available in the FIFO,
tvalid
is asserted. When
tready
is returned active, the FIFO is read
and the new pixel is again denoted by the
tvalid
being active. Thus, the
tvalid
is
asserted except when there is no valid data available from the FIFO. The FIFO will only begin
filling if the downstream core cannot accept data as fast as it is coming in from the video
bus. This will happen, for example, if the AXI4-Stream clock,
aclk
, is slower than the video
clock. In this case, during the active portion of each line, pixels will be coming into the FIFO
faster than they can be sent out on the AXI4-Stream bus. Thus the FIFO will begin to fill.
Usually the FIFO will empty at the end of the active line when the downstream core is still
taking pixels, but the incoming video data is in the horizontal blanking period.
At the end of each line, the EOL must be flushed through from the FIFO to the output
registers. This is done so that the downstream core can access the complete line without
having to wait through the horizontal blanking period for new pixels to push the EOL out.
This flushing requirement presents a challenge since this occurs during horizontal blanking,
meaning that no data is coming into the FIFO. It requires generation of invalid pixels to flush
out the valid pixels. Since no inactive pixels are allowed on the AXI4-Stream bus, these
invalid pixels must be swallowed by the core prior to the output.
Flushing of the EOL is accomplished by reading from the FIFO whenever it is not empty or
when it is empty and the last pixel has the EOF (
tlast
) flag set (assuming AXI4-Stream bus
is not applying backpressure). In other words, read the FIFO until it is empty, and beyond
when the EOL is present. When the FIFO is empty, and the last pixel has been read (the EOL
pixel) the FIFO will mark subsequent pixels as invalid, but the EOL will continue to
propagate to the output. Valid pixels get sent out on the AXI-4 Stream bus, invalid pixels do
not. In this way, invalid pixels are swallowed before they get to the AXI-4 Stream bus.