Video In to AXI4-Streamt
4
PG043 April 24, 2012
Product Specification
Introduction
The Xilinx LogiCORE™ IP Video In to
AXI4-Stream core is designed to interface from
a video source (clocked parallel video data with
synchronization signals - active video with
either syncs, blanks or both) to the AXI4-Stream
Video Protocol Interface. This core works in
conjunction with the timing detector portion of
the Xilinx Video Timing Controller (VTC) core.
This core provides a bridge between a video
input and video processing cores with
AXI4-Stream Video Protocol interfaces.
Features
• Video (clocked parallel video data with
synchronization signals - active video with
either syncs, blanks or both) input
• AXI4-Stream Video Protocol interface for
output
• Interface to Xilinx Video Timing Controller
core for video timing generation
• Handles asynchronous clock boundary
crossing between video clock domain and
AXI4-Stream clock domain
• Selectable FIFO depth from 64 -8192
locations
• Selectable input data width of 8-64 bits
LogiCORE IP Video In to
AXI4-Stream v1.0
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(
)
Zynq-7000, Artix-7, Virtex
®
-7, Kintex
®
-7,
Virtex-6, Spartan
®
-6
Supported User
Interfaces
AXI4-Stream
(
)
Resources
See
Provided with Core
Documentation
Product Guide
Design Files
Verilog Source Code
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
Not Provided
Simulation
Models
Verilog Source Code
Tested Design Tools
Design Entry
Tools
ISE 14.1
Simulation
(
Mentor Graphics ModelSim, Xilinx® ISim
Synthesis Tools
Xilinx Synthesis Technology (XST)
Support
Provided by Xilinx, Inc.
1. For a complete listing of supported devices, see the
for this core.
2. Video protocol as defined in the
Video IP: AXI Feature
Adoption
section of
.
3. For the supported versions of the tools, see the
ISE Design
Suite 14: Release Notes Guide
.
