Xilinx LogiCORE IP Video In to AXI4-Stream v1.0, Product Manual

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Video In to AXI4-Stream www.xilinx.com 18
PG043 April 24, 2012
Chapter 4
Designing with the Core
General Design Guidelines
The video inputs of the Video In to AXI4 Stream core should be connected to the input
video source, for example, a DVI interface chip that produces parallel video data, and timing
signals. Not all of the timing signals are required by this core, however it also passes these
signals out to a Xilinx Video Timing Controller which, depending on its configuration may
require certain timing signals. The set of timing signals used should be those required by
the VTC detector. See the PG016 Video Timing Controller Product Guide for more details.
For the Video In to AXI4 Stream core, the data enable is always required. Also, either a
vertical sync or a vertical blank input is required.
The main output of the core is a master AXI-4 Stream bus, that connects to downstream
video processing blocks as shown in Figure 4-1 . The master and slave interfaces share a
common clock, reset and clock enable.
As shown in Figure 4-1 , the Video In to AXI4 Stream Core is generally used in conjunction
with the Video Timing Controller which detects the video timing parameter used by
downstream processing blocks.