PZ-TIO Manual
Version 1.01
© 2022 XIA LLC
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JP802, JP803
Select one of the input clocks for the clock PLL chip as:
- external (MMCX CLK IN)
- PTP PHY
- FPGA Fabric (e.g. derived from White Rabbit)
JP622
Selects the input clock for the PTP PHY
- local oscillator
- clock PLL chip
10.5 LEDs
The PZ-TIO has LED indicators for the following
D103_A,_B,_C near the SFP connectors to indicate a link [orange]
LEDs built into J1 to indicate PS Ethernet link and activity [green, orange]
D141 near the UART/USB connector to indicate a link [orange]
D400 [green]
When blinking, Zynq PL is powered and configured
When on, the White Rabbit interface is fully synchronized (WR_valid)
D402 [yellow]
connected to FPGA logic, indicates “run in progress”
D401 [red]
set by PS program, indicates “error”
10.6 IEEE 1588 Precision Timing Protocol
While traditionally electronics use dedicated clock and trigger connections to synchronize
multiple units, the PZ-TIO has the option to instead use the IEEE 1588 Precision Timing
Protocol (PTP) to synchronize modules. Each PZ-TIO operates from its local clock, but
clock frequencies and timestamps are adjusted by software that uses special PTP messages
exchanged through the data network. With suitable network configurations, this can
achieve sub-nanosecond precision.
10.6.1 Overview
The Zynq SoC used as the PZ-TIO’s processor has a number of PTP functions built into
its standard Ethernet controller. With suitable Linux kernel options and PTP stack software
(see below), the Zynq PTP clock can be synchronized to other PTP nodes in the network
with a precision of ~1500 ns. However, as there are no useful connections between the
Zynq PTP clock controller and FPGA fabric, this is of limited use for the logic. This “PTP
software
timestamping” operation has not been tested on current hardware or firmware.
Therefore, the PZ-TIO implements the following alternate PTP functions:
Redirect Ethernet data from Zynq PS to a secondary Ethernet PHY.
Perform PTP time stamping in the secondary Ethernet PHY.
Generate a programmable PTP clock that can be used to clock the FPGA processing.
Generate programmable PTP triggers for internal and external use, e.g. a pulse per
second signal or an enable signal that allows data acquisition to begin at a specific
time.
