PZ-TIO Manual
Version 1.01
© 2022 XIA LLC
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10 Hardware Information
10.1 Board Architecture
Figure 10-1: Block diagram of the PZ-TIO. Blue lines indicate data connections, green clocks or
triggers. Dashed lines are available but currently not implemented (and therefore not fully tested
or guaranteed to function). Black dotted lines indicate internal data connections in the Zynq.
The PZ-TIO carrier board is primarily a desktop GPIO switchboard for the PicoZed. The
logic in the PicoZed Zynq FPGA side (PL) can be programmed to route signals from input
to outputs (some are bidirectional), and to compute results from the signals that are visible
to the Linux OS on the PicoZed ARM side (PS). User control is implemented via C
programs executed on the ARM section of the Zynq, with UART or Ethernet access from
a host PC or other device on the network. The PZ-TIO supports network time
synchronization, which makes available PTP or White Rabbit time and/or triggers to the
FPGA logic.
10.2 Connections
10.2.1 Data Connectors
The PZ-TIO has the following data connectors
P100_A SFP cage, connected to FPGA fabric and GTX pins. Currently unused
