Winbond W83627F, Manual

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W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
- 50 - Revision 1.0
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3
is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the
bit is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position
as the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
TABLE 4-2 WORD LENGTH DEFINITION
DLS1 DLS0 DATA LENGTH
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
4.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
1
2
3 4
5
6 7 0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)